Prosecution Insights
Last updated: April 19, 2026
Application No. 18/506,375

SYSTEMS AND METHODS FOR REDUCING SEMICONDUCTOR DEVICE DELAMINATION

Non-Final OA §102
Filed
Nov 10, 2023
Examiner
TRAPANESE, WILLIAM C
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Micro Devices, Inc.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
3y 3m
To Grant
98%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
479 granted / 626 resolved
+8.5% vs TC avg
Strong +21% interview lift
Without
With
+21.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
30 currently pending
Career history
656
Total Applications
across all art units

Statute-Specific Performance

§101
10.8%
-29.2% vs TC avg
§103
54.6%
+14.6% vs TC avg
§102
24.2%
-15.8% vs TC avg
§112
3.1%
-36.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 626 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Analysis for Independent Claims (Dependent Claim Analysis will follow) Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 9, 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Deguchi et al. (hereinafter Deguchi, US 2019/0295930). In regards to independent claim 1, Deguchi teaches a semiconductor device, comprising: a top barrier layer (Deguchi, Fig. 7, Item BR2, [0111], “barrier conductor film BR2”) deposited on top of a metal layer plating (Deguchi, Fig. 7, Item AM1, [0111], “an aluminum (Al)-containing conductive film AM1”) a bottom barrier layer (Deguchi, Fig. 7, Item BR1, [0111], “barrier conductor film BR1”); and dielectric material deposited on top of the top barrier layer and adjacent to the metal layer and the bottom barrier layer (Deguchi, Fig. 7, Item PV1, [0110], “an insulating film PV1”). In regards to independent claim 9, Deguchi teaches a semiconductor device package, comprising: a barrier layer deposited on top of a metal redistribution layer (Deguchi, Fig. 7, Item BR1 on AM1, [0111], “barrier conductor film BR2”, AM1 is metal redistribution layer as it allows external access to CP as seen by the probe in Fig. 9); dielectric material deposited on top of the barrier layer absent planarization of the metal redistribution layer (Deguchi, Fig. 7, Item PV1 on BR2, [0110], “an insulating film PV1”); and a die resting on top of a carrier and electrically connected to the metal redistribution layer (Deguchi, Fig. 2 Item CP “semiconductor device” on Item DP “die pad”, Fig. 6 CP Item PD connected to circuit via V7). In regards to independent claim 15, Deguchi teaches a method comprising: depositing a top barrier layer on top of a metal layer plating a bottom barrier layer (Deguchi, Fig. 7, Item BR1, [0111], “barrier conductor film BR2”, [0149])); and depositing dielectric material on top of the top barrier layer and adjacent to the metal layer and the bottom barrier layer (Deguchi, Fig. 7, Item PV1, [0110], “an insulating film PV1”, [0149]). Claim Analysis for Dependent Claims Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 2-8, 10-14, 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Deguchi. In regards to dependent claim 2, Deguchi teaches wherein the top barrier layer, the metal layer, and the bottom barrier layer are subjected to etching (Deguchi, [0150]). In regards to dependent claim 3, Deguchi teaches a die exposed by the etching (Deguchi, Fig. 17, IL8). In regards to dependent claim 4, Deguchi teaches wherein the dielectric material is further deposited on top of the die (Deguchi, Fig. 17, IL8, PV1). In regards to dependent claim 5, Deguchi teaches additional dielectric material exposed by the etching (Deguchi, Fig. 17, IL8). In regards to dependent claim 6, Deguchi teaches wherein the dielectric material is further deposited on top of the additional dielectric material (Deguchi, Fig. 17, IL8, PV1). In regards to dependent claim 7, Deguchi teaches wherein the top barrier layer is deposited on top of the metal layer absent planarization of the metal layer (Deguchi, Fig. 7, Item BR1, [0111], “barrier conductor film BR2”, [0149])). In regards to dependent claim 8, Deguchi teaches wherein the metal layer corresponds to a redistribution layer of the semiconductor device (Deguchi, Fig. 7, Item BR1 on AM1, [0111], “barrier conductor film BR2”, AM1 is metal redistribution layer as it allows external access to CP as seen by the probe in Fig. 9). In regards to dependent claim 10, Deguchi teaches: an additional barrier layer plated by the metal redistribution layer, wherein the barrier layer, the metal redistribution layer, and the additional barrier layer are subjected to etching, and the dielectric material is further deposited adjacent to the metal redistribution layer and the additional barrier layer (Deguchi, Fig. 7, Item BR1, BR2, AM1, [0111], [0150], “barrier conductor film BR2”, AM1 is metal redistribution layer as it allows external access to CP as seen by the probe in Fig. 9). In regards to dependent claim 11, Deguchi teaches wherein the die is exposed by the etching (Deguchi, Fig. 17, IL8). In regards to dependent claim 12, Deguchi teaches wherein the dielectric material is further deposited on top of the die (Deguchi, Fig. 17, IL8, PV1). In regards to dependent claim 13, Deguchi teaches additional dielectric material exposed by the etching (Deguchi, Fig. 17, IL8). In regards to dependent claim 14, Deguchi teaches wherein the dielectric material is further deposited on top of the additional dielectric material (Deguchi, Fig. 17, IL8, PV1). In regards to dependent claim 16, Deguchi teaches subjecting the top barrier layer, the metal layer, and the bottom barrier layer to etching (Deguchi, [0150]). In regards to dependent claim 17, Deguchi teaches wherein the etching exposes a die (Deguchi, Fig. 17, IL8). In regards to dependent claim 18, Deguchi teaches wherein depositing the dielectric material further deposits the dielectric material on top of the die (Deguchi, Fig. 17, IL8, PV1). In regards to dependent claim 19, Deguchi teaches wherein the etching exposes additional dielectric material (Deguchi, Fig. 17, IL8). In regards to dependent claim 20, Deguchi teaches wherein depositing the dielectric material further deposits the dielectric material on top of the additional dielectric material (Deguchi, Fig. 17, IL8 PV1). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C TRAPANESE whose telephone number is (571)270-3304. The examiner can normally be reached Monday - Friday 7am-12pm & 8pm-10pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Nov 10, 2023
Application Filed
Jan 10, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
98%
With Interview (+21.4%)
3y 3m
Median Time to Grant
Low
PTA Risk
Based on 626 resolved cases by this examiner. Grant probability derived from career allow rate.

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