Attorney’s Docket Number: P231115US00
Filing Date: 11/10/2023
Claimed Priority Date: 07/22/2020 (CON of 16/964,169 now PAT 11,930,669)
09/27/2019 (371 of PCT/CN2019/108526)
Applicants: Zhang et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Application filed on 11/10/2023.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The application serial no. 18/506,402 filed on 11/10/2023 has been entered. Accordingly, pending in this Office action are claims 1-10.
Specification
The disclosure is objected to because of the following informalities:
- Par. [0088], L. 4-5: amend to -- the thickness of the second gate insulation layer 16 -- in accordance with the disclosure at, e.g., Par. [0074], L. 3: “a second gate insulation layer 16”.
- Par. [0099], L. 1-2: amend to -- the anode layer 111 is the anode layer of the red sub-pixel adjacent to the imaging pinhole, and the anode layer 111 is electrically connected to the light shielding layer 19 -- in accordance with the disclosure at, e.g., Par. [0092], L. 5: “an anode layer 111”.
Appropriate corrections are required.
Claim Objections
Claims 1 and 10 are objected to because of the following informalities:
- Claim 1, L. 4-5: amend to -- wherein the display panel further comprises an organic light emitting layer formed in the opening regions; pixels in the display panel comprise red sub-pixels, green sub-pixels and blue sub-pixels--, for clarity.
- Claim 10, L. 3: amend to -- the light shielding layer comprises an imaging pinhole--, for clarity.
Appropriate corrections are required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Examiner’s note: The claims are replete with anteceding basis issues, inconsistent terminology for identifying same features throughout the claims, and inconsistent use of singular/plural when referring to features, thus affecting the clarity of the claims and rendering the claims indefinite. In the interest of compact prosecution, Applicant is requested to thoroughly review ALL claims to resolve said issues (some of which being identified below), so as to conform to current U.S. practice standards.
Claim 1 recites the limitations “the reset circuit is electrically connected to the control terminal of the drive circuit and the first light emitting voltage applying electrode of the light emitting element” at L. 17-19, and “under the control of the reset control signal” at L. 20-21. There is insufficient antecedent basis for these limitations in the claim. For the purpose of examination, the claim will be construed as reciting -- the reset circuit is electrically connected to the control terminal of the drive circuit and a first light emitting voltage applying electrode of the light emitting element--, and --under the control of a reset control signal--, respectively, until further clarifications are provided by applicant.
Claims 2-10 depend from claim 1 thus inherit the deficiencies identified supra.
Claim 2 recites the limitations “and the power supply voltage terminal for supplying the power supply voltage signal VDD” at L. 3-4, and “the first electrode of the first reset transistor is configured to be electrically connected to the first reset power supply terminal to receive the first reset signal, the gate of the first reset transistor is configured to be electrically connected to the first reset control signal line to receive the first reset control sub-signal; the first electrode of the second reset transistor is configured to be electrically connected to the second reset power supply terminal to receive the second reset signal, and the gate of the second reset transistor is configured to be electrically connected to the second reset control signal line to receive the second reset control sub-signal.” at L. 13-20. There is insufficient antecedent basis for these limitations in the claim. For the purpose of examination, the claim will be construed as reciting -- and a power supply voltage terminal for supplying a power supply voltage signal VDD --, and -- a first electrode of the first reset transistor is configured to be electrically connected to a first reset power supply terminal to receive a first reset signal, a gate of the first reset transistor is configured to be electrically connected to a first reset control signal line to receive a first reset control sub-signal; a first electrode of the second reset transistor is configured to be electrically connected to a second reset power supply terminal to receive a second reset signal, and a gate of the second reset transistor is configured to be electrically connected to a second reset control signal line to receive a second reset control sub-signal.--, respectively, until further clarifications are provided by applicant.
Claim 3 recites the limitations “configured to write the data voltage on the data line Vd to the storage circuit under the control of the scan signal” at L. 3-4, and “electrically connected to the control terminal of the drive circuit and the power supply voltage terminal” at L. 5-6. There is insufficient antecedent basis for these limitations in the claim. For the purpose of examination, the claim will be construed as reciting --configured to write a data voltage on a data line Vd to the storage circuit under the control of a scan signal--, and --electrically connected to the control terminal of the drive circuit and a power supply voltage terminal--, respectively, until further clarifications are provided by applicant.
Claim 5 recites the limitation “the light shielding layer is provided on a light incoming side of the fingerprint recognition sensor” at L. 3-4. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the claim will be construed as reciting -- the light shielding layer is provided on a light incoming side of a fingerprint recognition sensor--, until further clarifications are provided by applicant.
Claim 8 recites the limitation “wherein the second source-drain metal layer further comprises the imaging pinhole” at L. 1-2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the claim will be construed as reciting --wherein the second source-drain metal layer further comprises an imaging pinhole--, until further clarifications are provided by applicant.
Claim 9 recites the limitation “wherein the portion comprised in the pattern of the light shielding layer other than the conductive intermediate-connection pattern portions” at L. 1-2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the claim will be construed as reciting -- wherein a portion comprised in the pattern of the light shielding layer other than until further clarifications are provided by applicant.
Claim 10 recites the limitations “a minimum distance between the imaging pinhole and the organic light emitting layer in the red sub-pixel is less than a minimum distance between the imaging pinhole and the organic light emitting layer in the green sub-pixel; the minimum distance between the imaging pinhole and the organic light emitting layer in the red sub-pixel is less than a minimum distance between the imaging pinhole and the organic light emitting layer in the blue sub-pixel.” at L. 8-13. There is insufficient antecedent basis for these limitations in the claim and it is unclear which particular red, green, or blue sub-pixel are the limitations directed to. For the purpose of examination, the claim will be construed as reciting a minimum distance between the imaging pinhole and the organic light emitting layer in the red sub-pixels is less than a minimum distance between the imaging pinhole and the organic light emitting layer in the green sub-pixels; the minimum distance between the imaging pinhole and the organic light emitting layer in the red sub-pixels is less than a minimum distance between the imaging pinhole and the organic light emitting layer in the blue sub-pixels--, in accordance with the claim language introduced in claim 1 at L. 5-6 “red sub-pixels, green sub-pixels and blue sub-pixels”, until further clarifications are provided by applicant.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yi et al. (US2019/0131371).
Regarding Claim 1, Yi (see, e.g., Figs. 1-9) shows all aspects of the instant invention, including a display panel (e.g., display apparatus 1), comprising a base substrate (e.g., substrate 10), a light shielding layer (see, e.g., Par. [0093]: light-shielding member 130) and a pixel definition layer (e.g., insulating layer 16) which are provided on the base substrate in turn, opening regions (e.g., openings OP1-OP3) arranged in an array are formed on the pixel definition layer
- wherein the display panel further comprises an organic light emitting layer (e.g., organic light-emitting layer having portions 140a-c) formed in the opening region
- pixels in the display panel comprises red sub-pixels (e.g., PX1 is a red pixel R emitting red light), green sub-pixels (e.g., PX3 is a green pixel G emitting green light) and blue sub-pixels (e.g., PX2 is a blue pixel B emitting blue light)
- wherein each one of the red sub-pixels, green sub-pixels and blue sub-pixels comprises a pixel circuit (see, e.g., Figs. 3-5: circuit of a pixel PX), the pixel circuit comprising:
- a light emitting element (e.g., organic light-emitting device OLED), a drive circuit (e.g., T1), a first light emitting control circuit (e.g., T5), and a second light emitting control circuit (e.g., T6)
- wherein the drive circuit comprises a control terminal (e.g., G1), a first terminal (e.g., S1), and a second terminal (e.g., D1), and is configured to provide the light emitting element with a driving current that drives the light emitting element to emit light (see, e.g., Par: [0063])
- wherein the pixel circuit further comprises:
- a data writing circuit (e.g., T2), a storage circuit (e.g., Cst), a threshold compensation circuit (e.g., T3) and a reset circuit (e.g., T4,T7)
- the reset circuit is electrically connected to the control terminal of the drive circuit (e.g., D4 of T4 and G1 of T1 are electrically connected) and the first light emitting voltage applying electrode of the light emitting element (e.g., S7 of T7 and anode of OLED are electrically connected), and is configured to reset the control terminal of the drive circuit and the first light emitting voltage applying electrode of the light emitting element under the control of the reset control signal (see, e.g., Par: [0066],[0070]).
Regarding Claim 2, Yi (see, e.g., Figs: 3-5) shows that:
- the first light emitting control circuit (e.g., T5) is connected to the first terminal of the drive circuit (e.g., S1) and the power supply voltage terminal for supplying the power supply voltage signal VDD (e.g., power line PL for transmitting power source voltage ELVDD), and is configured to control the drive circuit to be connected to or disconnected from the power supply voltage terminal for supplying the power supply voltage signal VDD (see, e.g., Par: [0063],[0067])
- the second light emitting control circuit (e.g., T6) is electrically connected to the second terminal of the drive circuit (e.g., D1) and the first light emitting voltage applying electrode of the light emitting element (e.g., anode of OLED), and is configured to control the drive circuit to be connected to or disconnected from the light emitting element (see, e.g., Par: [0063],[0068])
- wherein the reset circuit further comprises a first reset transistor (e.g., T4) and a second reset transistor (e.g., T7)
- the first electrode of the first reset transistor (e.g., S4 of T4) is configured to be electrically connected to the first reset power supply terminal to receive the first reset signal (e.g., connected to initialization line VL supplying initialization voltage Vint), the gate of the first reset transistor (e.g., G4 of T4) is configured to be electrically connected to the first reset control signal line to receive the first reset control sub-signal (e.g., connected to scan line GIL supplying scan signal GI) (see, e.g., Par. [0066])
- the first electrode of the second reset transistor (e.g., D7 of T7) is configured to be electrically connected to the second reset power supply terminal to receive the second reset signal (e.g., connected to initialization line VL supplying initialization voltage Vint), and the gate of the second reset transistor (e.g., G7 of T7) is configured to be electrically connected to the second reset control signal line to receive the second reset control sub-signal (e.g., connected to scan line GBL supplying scan signal GB) (see, e.g., Par. [0070]).
Regarding Claim 3, Yi (see, e.g., Figs: 3-5) shows that:
- the data writing circuit (e.g., T2) is electrically connected to the first terminal of the drive circuit (e.g., D2 of T2 and S1 of T1 are electrically connected), and is configured to write the data voltage on the data line Vd (e.g., data signal DATA on data line DL) to the storage circuit under the control of the scan signal (e.g., scan signal GW) (see, e.g., Par. [0072])
- the storage circuit (e.g., Cst) is electrically connected to the control terminal of the drive circuit (e.g., G1) and the power supply voltage terminal (e.g., PL), and is configured to store the data voltage (see, e.g., Par. [0072])
- the threshold compensation circuit (e.g., T3) is electrically connected to the control terminal of the drive circuit (e.g., D3 of T3 and G1 are electrically connected) and the second terminal of the drive circuit (e.g., S3 of T3 and D1 are electrically connected), and is configured to perform threshold compensation on the drive circuit (see, e.g., Par. [0065]).
Claims 1-4, 6-7, and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Na et al. (US2020/0312941).
Regarding Claim 1, Na (see, e.g., Figs. 1-8) shows all aspects of the instant invention, including a display panel (e.g., display apparatus), comprising a base substrate (e.g., substrate 110), a light shielding layer (see, e.g., Par. [0122]-[0126]: metal layer comprising line PL2, connecting electrode CM, and shield portion SP) and a pixel definition layer (e.g., pixel defining layer 119) which are provided on the base substrate in turn, opening regions (e.g., openings OP1-OP3) arranged in an array are formed on the pixel definition layer
- wherein the display panel further comprises an organic light emitting layer (e.g., organic light-emitting layer 222 having portions B,G,R) formed in the opening region
- pixels in the display panel comprises red sub-pixels, green sub-pixels and blue sub-pixels (see, e.g., Fig. 3 and Par. [0035],[0058]: PX denote a sub-pixel emitting one of red light R, green light G, or blue light B)
- wherein each one of the red sub-pixels, green sub-pixels and blue sub-pixels comprises a pixel circuit (see, e.g., Figs. 2B and 4-8: circuit of a pixel PX), the pixel circuit comprising:
- a light emitting element (e.g., organic light-emitting device OLED), a drive circuit (e.g., T1), a first light emitting control circuit (e.g., T5), and a second light emitting control circuit (e.g., T6)
- wherein the drive circuit comprises a control terminal (e.g., GE1), a first terminal (e.g., S1), and a second terminal (e.g., D1), and is configured to provide the light emitting element with a driving current that drives the light emitting element to emit light (see, e.g., Par: [0041])
- wherein the pixel circuit further comprises:
- a data writing circuit (e.g., T2), a storage circuit (e.g., Cst), a threshold compensation circuit (e.g., T3) and a reset circuit (e.g., T4,T7)
- the reset circuit is electrically connected to the control terminal of the drive circuit (e.g., D4 of T4 and GE1 of T1 are electrically connected) and the first light emitting voltage applying electrode of the light emitting element (e.g., S7 of T7 and anode of OLED are electrically connected), and is configured to reset the control terminal of the drive circuit and the first light emitting voltage applying electrode of the light emitting element under the control of the reset control signal (see, e.g., Par: [0050],[0054]).
Regarding Claim 2, Na (see, e.g., Figs. 2B and 4-8) shows that:
- the first light emitting control circuit (e.g., T5) is connected to the first terminal of the drive circuit (e.g., S1) and the power supply voltage terminal for supplying the power supply voltage signal VDD (e.g., power line PL for transmitting power source voltage ELVDD), and is configured to control the drive circuit to be connected to or disconnected from the power supply voltage terminal for supplying the power supply voltage signal VDD (see, e.g., Par: [0046]-[0047])
- the second light emitting control circuit (e.g., T6) is electrically connected to the second terminal of the drive circuit (e.g., D1) and the first light emitting voltage applying electrode of the light emitting element (e.g., anode of OLED), and is configured to control the drive circuit to be connected to or disconnected from the light emitting element (see, e.g., Par: [0046]-[0047])
- wherein the reset circuit further comprises a first reset transistor (e.g., T4) and a second reset transistor (e.g., T7)
- the first electrode of the first reset transistor (e.g., S4 of T4) is configured to be electrically connected to the first reset power supply terminal to receive the first reset signal (e.g., connected to initialization line VL supplying initialization voltage Vint), the gate of the first reset transistor (e.g., G4 of T4) is configured to be electrically connected to the first reset control signal line to receive the first reset control sub-signal (e.g., connected to scan line Sn-1 supplying scan signal SL-1) (see, e.g., Par. [0050])
- the first electrode of the second reset transistor (e.g., D7 of T7) is configured to be electrically connected to the second reset power supply terminal to receive the second reset signal (e.g., connected to initialization line VL supplying initialization voltage Vint), and the gate of the second reset transistor (e.g., G7 of T7) is configured to be electrically connected to the second reset control signal line to receive the second reset control sub-signal (e.g., connected to scan line Sn-1 supplying scan signal SL-1) (see, e.g., Par. [0054]).
Regarding Claim 3, Na (see, e.g., Figs. 2B and 4-8) shows that:
- the data writing circuit (e.g., T2) is electrically connected to the first terminal of the drive circuit (e.g., D2 of T2 and S1 of T1 are electrically connected), and is configured to write the data voltage on the data line Vd (e.g., data signal Dm on data line DL) to the storage circuit under the control of the scan signal (e.g., scan signal Sn) (see, e.g., Par. [0039]-[0040],[0047]-[0048])
- the storage circuit (e.g., Cst) is electrically connected to the control terminal of the drive circuit (e.g., GE1) and the power supply voltage terminal (e.g., PL), and is configured to store the data voltage (see, e.g., Par. [0040]-[0041])
- the threshold compensation circuit (e.g., T3) is electrically connected to the control terminal of the drive circuit (e.g., D3 of T3 and GE1 are electrically connected) and the second terminal of the drive circuit (e.g., S3 of T3 and D1 are electrically connected), and is configured to perform threshold compensation on the drive circuit (see, e.g., Par. [0049]).
Regarding Claim 4, Na (see, e.g., Figs. 7-8 and Par. [0122]-[0126]) discloses a metal layer comprising: line PL2 driving voltage ELVDD, connecting electrode CM connected to the S/D region of a TFT, and shield portion SP. Therefore, Na shows that a second source-drain metal layer (e.g., CM) is re-used as the light shielding layer, a pattern of the second source-drain metal layer comprises a power supply voltage pattern portion (e.g., PL2).
Regarding Claim 6, Na (see, e.g., Figs. 7-8 and Par. [0122]-[0126]) shows that the second source-drain metal layer (e.g., CM) further comprises a conductive connection pattern portion (e.g., contact hole CNT1).
Regarding Claim 7, Na (see, e.g., Figs. 7-8 and Par. [0082]) shows:
- an anode layer (e.g., pixel electrode 221) provided between the light shielding layer and the pixel definition layer, and a thin film transistor array layer provided between the base substrate and the anode layer (see, e.g., Fig. 7C)
- the thin film transistor array layer comprises a first source-drain metal layer (e.g., comprising source electrode SE and the drain electrode DE) and a semiconductor layer (e.g., semiconductor layer Act), the second source-drain metal layer (e.g., CM) is disposed over the first source-drain metal layer, and the anode layer is disposed over the light shielding layer.
Regarding Claim 9, Na (see, e.g., Figs. 7-8) shows that the portion comprised in the pattern of the light shielding layer other than the conductive intermediate-connection pattern portions forms a VDD signal functional layer (e.g., PL2).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose display panel with color AMOLED arrangements having features similar to the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
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