DETAILED ACTION
This Office action is in response to the election filed 20 April 2026. Claims 1-30 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-21 and 29-30, in the reply filed on 20 April 2026 is acknowledged.
Claims 22-28 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 20 April 2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation "the (222) crystal plane of the first oxide semiconductor layer" in line 3 and “the (400) crystal plane of the first oxide semiconductor layer” in line 5. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the presence of a (222) crystal plane and a (400) crystal plane of the first oxide semiconductor layer is assumed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-9, 11-13, 20-21, and 29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2014/0042437 A1 to Yamazaki (hereinafter “Yamazaki”).
Regarding independent claim 1, Yamazaki (Fig. 2B) discloses a thin film transistor comprising: an active layer 408 (¶ 0099); and a gate electrode 402 (¶ 0099) spaced apart from the active layer and partially overlapping the active layer (Fig. 2B); wherein the active layer includes: a first oxide semiconductor layer 408a (¶ 0101); and a second oxide semiconductor layer 408b (¶ 0101; or 408c in alternative interpretation) on the first oxide semiconductor layer, wherein the first oxide semiconductor layer 408a has an amorphous structure (¶ 0101) and the second oxide semiconductor layer 408b has a crystalline structure (¶ 0101).
Regarding claim 2, Yamazaki (Fig. 2B) discloses the thin film transistor of claim 1, wherein a ratio of crystal grains having a particle diameter of 1 nm or more in a cross-section of the second oxide semiconductor layer 408b (¶¶ 0074-75, ratio is greater than 0) is greater than a ratio of crystal grains having a particle diameter of 1 nm or more in a cross-section of the first oxide semiconductor layer 408a (¶ 0073 - 408a has “disordered atomic arrangement and no crystalline component” thus a ratio of 0).
Regarding claim 3, Yamazaki (Fig. 2B) discloses the thin film transistor of claim 1, wherein in a cross-sectional image of the first oxide semiconductor layer 408a taken by a transmission electron microscope, a ratio of crystal grains having a particle diameter of 1 nm or more is 10% or less based on a total area of a cross-section of the first oxide semiconductor layer (¶ 0073 - 408a has “disordered atomic arrangement and no crystalline component” thus has 10% or less crystal grains), and in a cross-sectional image of the second oxide semiconductor layer 408b taken by the transmission electron microscope, a ratio of crystal grains having a particle diameter of 1 nm or more is 50% or more based on a total area of a cross-section of the second oxide semiconductor layer (¶ 0074).
Regarding claim 4, Yamazaki (Fig. 2B) discloses the thin film transistor of claim 1, wherein the second oxide semiconductor layer 408b includes a crystal grain having a particle diameter in a range of 0.5 nm to 50 nm (¶¶ 0074-75).
Regarding claim 5, Yamazaki (Fig. 2B) discloses the thin film transistor of claim 1, wherein the first oxide semiconductor layer 408a includes at least one of an InZnO-based oxide semiconductor material, an InGaZnO-based oxide semiconductor material, an InSnO-based oxide semiconductor material, an InGaZnSnO-based oxide semiconductor material (¶ 0118), GaZnSnO-based oxide semiconductor material (¶ 0118), or GaZnO-based oxide semiconductor material (¶ 0118).
Regarding claim 7, Yamazaki (Fig. 2B) discloses the thin film transistor of claim 1, wherein the second oxide semiconductor layer 408b includes at least one of ZnO-based oxide semiconductor material, InZnO-based oxide semiconductor material (¶ 0120), InGaZnO-based oxide semiconductor material, SnO-based oxide semiconductor material, InGaO-based oxide semiconductor material, InSnO-based oxide semiconductor material, InGaZnSnO-based oxide semiconductor material, GaZnSnO-based oxide semiconductor material, GaZnO-based oxide semiconductor material, GaO-based oxide semiconductor material, InO-based oxide semiconductor material, or InSnZnO-based oxide semiconductor material.
Regarding claim 8, Yamazaki (Fig. 2B) discloses the thin film transistor of claim 7, wherein the second oxide semiconductor layer 408c further includes a dopant doped in the second oxide semiconductor material, and the dopant includes at least one of aluminum, tin, or hafnium (¶ 0107).
Regarding claim 9, Yamazaki (Fig. 2B) discloses the thin film transistor of claim 1, wherein the second oxide semiconductor layer 408c is formed of an InGaO-based oxide semiconductor material (¶ 0118) doped with a dopant includes at least one of aluminum, tin, or hafnium (¶ 0107), and wherein the dopant is disposed in a crystal grain or at a boundary between the crystal grain in the second oxide semiconductor layer (dopants in a crystalline material are either disposed in a crystal grain or at a boundary between the crystal grain).
Regarding claim 11, Yamazaki (Fig. 2B) discloses the thin film transistor of claim 1, wherein the active layer 408 further includes a third oxide semiconductor layer 408c (¶ 0089) on the second oxide semiconductor layer 408b, the third oxide semiconductor layer 408c having an amorphous structure (¶ 0089).
Regarding claim 12, Yamazaki (Fig. 2B) discloses the thin film transistor of claim 1, wherein the active layer 408 is on a substrate 400 (¶ 0099), and the active layer 408 is between the substrate 400 and the gate electrode 402.
Regarding claim 13, Yamazaki (Fig. 2B) discloses the thin film transistor of claim 9, wherein the second oxide semiconductor layer 408b is between the first oxide semiconductor layer 408a and the gate electrode 402.
Regarding claim 20, Yamazaki (Fig. 2B) discloses the thin film transistor of claim 1, further comprising: a gate insulating layer 412 (¶ 0099) between the active layer 408 and the gate electrode 402, wherein the gate insulating layer includes at least one of silicon oxide, silicon nitride, a metal oxide, or a metal nitride (¶ 0133).
Regarding claim 21, Yamazaki (Fig. 2B) discloses the thin film transistor of claim 1. The limitations “wherein crystal grains grow from a bottom part, a side part, a middle part, and an upper part of the second oxide semiconductor layer” are merely product-by-process limitations that do not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
Regarding claim 29, Yamazaki (Figs. 11A-11B) discloses a display apparatus comprising the thin film transistor of claim 1 (Figs. 11A-11B; ¶¶ 0257-58).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 10, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki.
Regarding claim 6, Yamazaki (Fig. 2B) discloses the thin film transistor of claim 1, wherein the first oxide semiconductor layer 408a has a thickness of 1 nm to 10 nm (¶ 0123). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP § 2144.05(I).
Regarding claim 10, Yamazaki (Fig. 2B) discloses the thin film transistor of claim 1, wherein the second oxide semiconductor layer 408b has a thickness in a range of 10 nm to 50 nm (¶ 0124). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP § 2144.05(I).
Regarding claim 14, Yamazaki (Fig. 2B) discloses the thin film transistor of claim 1, however fails to expressly disclose wherein the gate electrode is on a substrate, and the gate electrode is between the substrate and the active layer. In a different embodiment, Yamazaki (Fig. 5A) discloses the gate electrode 402 is on a substrate 400, and the gate electrode 402 is between the substrate 400 and the active layer 408. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the gate electrode configuration as recited for the purpose of providing an art-recognized alternative TFT configuration, i.e., back gate TFT, as exemplified by Fig. 5A of Yamazaki.
Regarding claim 15, Yamazaki (Fig. 2B) discloses the thin film transistor of claim 11, however fails to expressly disclose wherein the first oxide semiconductor layer is between the second oxide semiconductor layer and the gate electrode. In a different embodiment, Yamazaki (Fig. 5A) discloses the first oxide semiconductor layer 408a is between the second oxide semiconductor layer 408b and the gate electrode 402. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the gate electrode configuration as recited for the purpose of providing an art-recognized alternative TFT configuration, i.e., back gate TFT, as exemplified by Fig. 5A of Yamazaki.
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki as applied to claims 1 and 13 above, and further in view of KR 10-2021-0027580 to Yang et al. (citations refer to the English machine translation attached herewith; hereinafter “Yang”).
Regarding claim 16, Yamazaki discloses the thin film transistor of claim 1, however fails to expressly disclose: wherein the second oxide semiconductor layer has a (222) crystal plane and a (400) crystal plane. In the same field of endeavor, Yang discloses a crystalline oxide semiconductor layer that has a (222) crystal plane and a (400) crystal plane (p. 4, para. 3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an oxide semiconductor layer as taught by Yang in the transistor of Yamazaki for the purpose of increasing electron mobility (p. 4, para. 2).
Regarding claim 17, Yamazaki discloses the thin film transistor of claim 13, however fails to expressly disclose: wherein the second oxide semiconductor layer has a peak intensity of a (222) crystal plane and a peak intensity of a (400) crystal plane, measured by X-ray diffraction analysis. In the same field of endeavor, Yang discloses a crystalline oxide semiconductor layer that has a peak intensity of a (222) crystal plane and a peak intensity of a (400) crystal plane, measured by X-ray diffraction analysis (p. 4, para. 3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an oxide semiconductor layer as taught by Yang in the transistor of Yamazaki for the purpose of increasing electron mobility (p. 4, para. 2).
Regarding claim 18, as best understood, Yamazaki and Yang disclose the thin film transistor of claim 17, however fail to expressly disclose: wherein the peak intensity of the (222) crystal plane of the second oxide semiconductor layer is 20 times or more of a peak intensity of the (222) crystal plane of the first oxide semiconductor layer, and the peak intensity of the (400) crystal plane of the second oxide semiconductor layer is 10 times or more of a peak intensity of the (400) crystal plane of the first oxide semiconductor layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the above peak intensity relationships between the second oxide semiconductor layer and the first oxide semiconductor layer, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F .2d 272, 205 USPQ 215 (CCPA 1980). Here, the peak intensity is considered a result effective variable because it is indicative of crystal formation in the layer, which affects electron mobility and performance of the transistor (see Yang, p. 10, first para.). Thus the ordinary artisan would have been motivated to modify the peak intensity relationship for the purpose of producing a transistor with high performance and efficiency.
Regarding claim 19, Yamazaki and Yang disclose the thin film transistor of claim 17, wherein the second oxide semiconductor layer further includes a (111) crystal plane (Yang, p. 4, para. 3).
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki as applied to claim 29 above, and further in view of US 2021/0036028 A1 to Kim et al. (hereinafter “Kim”).
Regarding claim 30, Yamazaki discloses the display apparatus of claim 29, and discloses the thin film transistor may be used in switching transistor or driving transistor applications (¶ 0244), however fails to expressly disclose further comprising: a plurality of pixels, each pixel including a display element and a pixel driving circuit configured to drive the display element, wherein the pixel driving circuit of at least one of the plurality of pixels includes a switching transistor connected with a gate line and a data line and configured to transmit a data voltage supplied to the data line to a driving transistor according to a scan signal supplied to the gate line, the driving transistor configured to control a magnitude of a current output to the display element in accordance with the data voltage transmitted through the switching transistor, and wherein at least one of the switching transistor and the driving transistor is constituted by the thin film transistor.
In the same field of endeavor, Kim (Figs. 2-3) discloses a plurality of pixels PX (¶ 0064), each pixel including a display element EL (¶ 0076) and a pixel driving circuit configured to drive the display element (Fig. 3; ¶ 0076), wherein the pixel driving circuit of at least one of the plurality of pixels includes a switching transistor SCT (¶ 0076) connected with a gate line SCLk and a data line DTLj and configured to transmit a data voltage supplied to the data line to a driving transistor DRT (¶0076) according to a scan signal supplied to the gate line, the driving transistor configured to control a magnitude of a current output to the display element in accordance with the data voltage transmitted through the switching transistor (¶ 0066). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the pixels and pixel driving circuit as taught by Kim, using the thin film transistor of Yamazaki in at least one of the switching transistor and driving transistor, in the display apparatus of Yamazaki for the purpose of forming a functional display in an art-recognized and conventional manner, as exemplified by Kim.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2020/0203534 A1 to Park et al. disclosing a thin film transistor including first and second oxide semiconductor layers; US 2014/0027762 A1 to Tsurume et al. disclosing a thin film transistor including an oxide semiconductor layer having a stacked layer structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
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CANDICE Y. CHAN
Examiner
Art Unit 2813
13 June 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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