DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-3 and 9-11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Reciting “the impermeable film being entirely separated from any lower wiring layer by the interlayer insulating film such that the impermeable film is electrically isolated from any conductive layer below the interlayer insulating film” introduces new matter into claims 1 and 9.
Nowhere in the specification was the impermeable film described as electrically isolated from any conductive layer below the interlayer insulating film. The specification actually describes the impermeable film as a part of the wiring layers for the semiconductor device: “An impermeable layer is formed in a layer to be the uppermost layer of the multi-layer wiring, and in the patterning, at least the enhancement type MOS transistor constituting the reference voltage circuit is laid out so as to cover the gate electrode and patterned to form the impermeable film. It is also possible to dispose the impermeable film not only on the gate electrode of the enhancement type MOS transistor but also on the gate electrode of the depletion type MOS transistor. As the impermeable layer, a metal wiring layer to be the uppermost layer can be used. Amorphous silicon formed by sputtering can also be used instead of metal” (¶¶28-29).
Claims 2-3 and 10-11 inherit this rejection for new matter.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3 and 9-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(Re Claims 1 and 9) As the impermeable film was not described as electrically isolated from any conductive layer, the structure of the device required by the limitation “the impermeable film being entirely separated from any lower wiring layer by the interlayer insulating film such that the impermeable film is electrically isolated from any conductive layer below the interlayer insulating film” is unclear.
During examination, “the impermeable film being entirely separated from any lower wiring layer by the interlayer insulating film such that the impermeable film is electrically isolated from any conductive layer below the interlayer insulating film” was read as “the impermeable film being separated from an adjacent lower wiring layer by the interlayer insulating film”.
Claims 2-3 and 10-11 inherit this rejection for indefiniteness.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshino (US 2014/0240038), Harada et al. (US 2016/0372465), Saito et al. (US 6,731,007), Sakamoto et al. (US 2002/0030268), Iwasaki (US 6,128,173), and Deguchi et al. (US 2018/0374795), all of record.
(Re Claim 1) Yoshino teaches a semiconductor device with a reference voltage circuit comprising: an enhancement type MOS transistor (12; Fig. 1) having a first channel region (¶24) including a first channel length direction and a first channel width direction (¶24), and polycrystalline silicon having P type conductivity (¶24) that serves as a first gate electrode (¶24); and a depletion type MOS transistor (11; Fig. 1) having a second channel region (¶24) including a second channel length direction and a second channel width direction (¶24), and polycrystalline silicon having N type conductivity (¶24) that serves as a second gate electrode.
Yoshino does not explicitly teach a semiconductor device polycrystalline silicon having P type conductivity that covers the first channel region and serves as a first gate electrode (¶24);
and polycrystalline silicon having N type conductivity that covers the second channel region and serves as a second gate electrode;
an impermeable film provided on the interlayer insulating film, disposed to cover the first gate electrode in a plan view, and the impermeable film being entirely separated from any lower wiring layer by the interlayer insulating film such that the impermeable film is electrically isolated from any conductive layer below the interlayer insulating film; and
a nitride film provided on the interlayer insulating film and the impermeable film, has an opening portion which is disposed above the impermeable film, covers a periphery of the impermeable film in the plan view, covers the depletion type MOS transistor without a gap in the plan view;
a polyimide film provided on the nitride film and the opening portion, and covering the opening portion without a gap, wherein:
the opening portion is provided larger than the first gate electrode in the plan view and smaller than the impermeable film.
Harada teaches a constant voltage circuit formed by connecting an enhancement type NMOS 101 and a depletion type NMOS 102. The gate electrodes 8 cover the first and second channel regions of the enhancement and depletion type NMOS, respectively (Fig. 1, ¶17).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to place a gate electrode over a corresponding channel region to create a functioning NMOS, and so would form the polycrystalline silicon gate electrodes of Yoshino over the corresponding channels, in the manner of Harada.
Saito teaches a vertically stacked semiconductor device, with two MOSFETs (respectively 3n and 3p; Fig. 1, col. 7 ln. 55-56). MOS 3n with gate electrode 3ng has an impermeable film (BP; formed from aluminum, which is impermeable to water; col. 17 ln. 13-15) that is disposed to cover the first gate electrode 3ng in a plan view and is provide on an interlayer insulating film (4d; Fig. 1) disposed on the first gate electrode. The interlayer insulating layer is provided on the underlying MOSFETs. The impermeable film is separated from an adjacent lower wiring layer (7C; Fig. 1) by the interlayer insulating layer (Fig. 1).
Furthermore, Saito teaches a nitride film (15; Fig. 1, col. 18 ln. 18-20) having an opening portion (16+the space occupied by BP; Fig. 1) that is disposed above the impermeable film (Fig. 1), covers a periphery of the impermeable film in the plan view (Fig. 1), and is provided smaller than the impermeable film (16 is narrower than BP; Fig. 1).
Furthermore, Saito teaches MOS 3p has a nitride film (15) that is directly provided on an interlayer insulating film (4d; Fig. 1) disposed on the second gate electrode (Fig. 1) and covers the MOS 3p without a gap in a plan view (Fig. 1).
A PHOSITA would know that in order to interact with the enhancement and depletion type MOS transistors of Harada in an integrated circuit configuration, an overlying interconnect structure is conventionally disposed over the transistors. Therefore, a PHOSITA would find it obvious to position the NMOS 101 and NMOS 102 of modified Yoshino to correspond with the positions of MOS 3n and MOS 3p of Saito, and build the structure of Saito over the transistors of modified Yoshino, to form connections for packaging (Saito: col. 18 ln. 25-28).
The impermeable film BP of Saito provided on the interlayer insulating film would then cover the first gate electrode (corresponding to 3ng of Saito) of the enhancement type MOS transistor in a plan view; and the nitride film of Saito would cover the depletion type MOS transistor without a gap in the plan view (Saito: across the level where the leader for 15a ends; Fig. 1).
Sakamoto teaches forming a polyimide film (50; Fig. 8, ¶¶94, 133) that encapsulates a wire bond (55A, Fig. 8).
A PHOSITA would find it obvious to form a polyimide film such that it encapsulates the wire bond of modified Yoshino (Yoshino: col. 18 ln. 24-28) and extends over the semiconductor device shown in Fig. 1 of Saito, in the manner taught by Sakamoto, in order to provide support to the wire bond.
This results in a polyimide film (Sakamoto: 50; Fig. 8) provided on the nitride film and the opening portion (Saito: 4a; Fig. 1), wherein the polyimide film covers, without a gap, the opening portion that is provided in the nitride film (polyimide film 50 of Sakamoto extends from left to right, without a gap, above the wire bond; Sakamoto: Fig. 8).
Iwasaki teaches the length and width of a gate electrode for an enhancement type NMOS are respectively 0.2 µm and 10 µm (col. 8 ln. 24-27).
Deguchi teaches that the minimum width for an opening portion (OP; Fig. 8) directly bonded with a wire is between 30 µm to 50 µm (¶137).
As either dimension of a gate electrode for an enhancement type MOS transistor are known to be smaller than the dimensions of an opening portion appropriate for direct wire bonding (Saito: col. 18 ln. 21-28), modified Yoshino in view of the dimensions from Iwasaki and Deguchi teaches the opening portion of the nitride film is provided larger than the first gate electrode. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
(Re Claim 2) Modified Yoshino teaches the semiconductor device with a reference voltage circuit according to claim 1, wherein the impermeable film is an uppermost wiring layer (Saito: Fig. 1).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshino (US 2014/0240038), Harada et al. (US 2016/0372465), Saito et al. (US 6,731,007), Sakamoto et al. (US 2002/0030268), Iwasaki (US 6,128,173), and Deguchi et al. (US 2018/0374795) all of record, as applied respectively to claim 1 above, and further in view of Fernandes et al. (US 5,310,626) of record.
(Re Claim 3) Modified Yoshino teaches the semiconductor device with a reference voltage circuit according to claim 1, but does not explicitly teach the semiconductor device wherein the impermeable film is amorphous silicon.
Fernandes teaches that amorphous silicon is a material that can be used to form a conductive layer (col. 6 ln. 1-6).
Modified Yoshino discloses the claimed invention except that a metal (Saito: col. 37 ln. 28-35) is used for an impermeable film instead of amorphous silicon. Fernandes shows that amorphous silicon is a functional equivalent in the art. Therefore, because these two materials were art-recognized alternatives at the time the invention was made, one of ordinary skill in the art would have found it obvious to substitute amorphous silicon for metal when forming an impermeable film. The use of a known material for its known properties is prima facie obvious. See MPEP 2143(B).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshino (US 2014/0240038), and Saito et al. (US 6,731,007), Sakamoto et al. (US 2002/0030268), Iwasaki (US 6,128,173), and Deguchi et al. (US 2018/0374795), all of record.
(Re Claim 9) Yoshino teaches a semiconductor device with a reference voltage circuit comprising: an enhancement type MOS transistor (12; Fig. 1) having polycrystalline silicon of P type conductivity (¶24), as a first gate electrode; and a depletion type MOS transistor (11; Fig. 1) having polycrystalline silicon of N type conductivity (¶24), as a second gate electrode.
Yoshino does not explicitly teach a semiconductor device comprising:
an interlayer insulating film provided on the enhancement type MOS transistor and the depletion type MOS transistor, and
an impermeable film provided on the interlayer insulating film, disposed to cover the first gate electrode in a plan view, and the impermeable film being entirely separated from any lower wiring layer by the interlayer insulating film such that the impermeable film is electrically isolated from any conductive layer below the interlayer insulating film; and
a nitride film provided on the interlayer insulating film and the impermeable film, has an opening portion which is disposed above the impermeable film, covers a periphery of the impermeable film in the plan view, covers the depletion type MOS transistor without a gap in the plan view; and
a polyimide film provided on the nitride film and the opening portion, and covering the opening portion without a gap,
wherein:
the opening portion is provided larger than the first gate electrode in the plan view and smaller than the impermeable film.
Saito teaches a vertically stacked semiconductor device, with two MOSFETs (respectively 3n and 3p; Fig. 1, col. 7 ln. 55-56). MOS 3n with gate electrode 3ng has an impermeable film (BP; formed from aluminum, which is impermeable to water; col. 17 ln. 13-15) that is disposed to cover a first gate electrode 3ng in a plan view, and provided on an interlayer insulating film (4d; Fig. 1).
Furthermore, Saito teaches a nitride film (15; Fig. 1, col. 18 ln. 18-20) having an opening portion (16+the space occupied by BP; Fig. 1) which is disposed above the first gate electrode in a cross-section view (Fig. 1) and includes the first gate electrode in a plan view (as it overlaps with the gate electrode 3ng; Fig. 1) and is provided smaller than the impermeable film (16 is narrower than BP; Fig. 1), and is provided to cover a periphery of the impermeable film (Fig. 1).
Furthermore, Saito teaches MOS 3p has a nitride film (15) provided on the interlayer insulating film (4d; Fig. 1) and the impermeable film, has an opening portion (16+the space occupied by BP; Fig. 1) which is disposed above the impermeable film, covers a periphery of the impermeable film in the plan view (Fig. 1), and covers the MOS 3p without a gap in a plan view (Fig. 1), and is provided smaller than the impermeable film (16 is narrower than BP; Fig. 1). The interlayer insulating layer is provided on the underlying MOSFETs. The impermeable film is separated from an adjacent lower wiring layer (7C; Fig. 1) by the interlayer insulating layer (Fig. 1).
A PHOSITA would know that in order to interact with the enhancement and depletion type MOS transistors of Harada in an integrated circuit configuration, an overlying interconnect structure is conventionally disposed over the transistors. Therefore, a PHOSITA would find it obvious to position the NMOS 101 and NMOS 102 of modified Yoshino to correspond with the positions of MOS 3n and MOS 3p of Saito, and build the structure of Saito over the transistors of modified Yoshino, to form connections for packaging (Saito: col. 18 ln. 25-28).
The impermeable film BP of Saito provided on the interlayer insulating film would then cover the first gate electrode (corresponding to 3ng of Saito) of the enhancement type MOS transistor in a plan view; and the nitride film of Saito would cover the depletion type MOS transistor without a gap in the plan view (Saito: across the level where the leader for 15a ends; Fig. 1).
Sakamoto teaches forming a polyimide film (50; Fig. 8, ¶¶94, 133) that encapsulates a wire bond (55A, Fig. 8).
A PHOSITA would find it obvious to form a polyimide film such that it encapsulates the wire bond of modified Yoshino (Yoshino: col. 18 ln. 24-28) and extends over the semiconductor device shown in Fig. 1 of Saito, in the manner taught by Sakamoto, in order to provide support to the wire bond.
This results in a polyimide film (Sakamoto: 50; Fig. 8) provided on the nitride film and the opening portion (Saito: 4a; Fig. 1), wherein the polyimide film covers, without a gap, the opening portion that is provided in the nitride film (polyimide film 50 of Sakamoto extends from left to right, without a gap, above the wire bond; Sakamoto: Fig. 8).
Iwasaki teaches the length and width of a gate electrode for an enhancement type NMOS are respectively 0.2 µm and 10 µm (col. 8 ln. 24-27).
Deguchi teaches that the minimum width for an opening portion (OP; Fig. 8) directly bonded with a wire is between 30 µm to 50 µm (¶137).
As either dimension of a gate electrode for an enhancement type MOS transistor are known to be smaller than the dimensions of an opening portion appropriate for direct wire bonding (Saito: col. 18 ln. 21-28), modified Yoshino in view of the dimensions from Iwasaki and Deguchi teaches the opening portion of the nitride film is provided larger than the first gate electrode. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
(Re Claim 10) Modified Yoshino teaches the semiconductor device with a reference voltage circuit according to claim 9, wherein the impermeable film is an uppermost wiring layer (Saito: Fig. 1).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshino (US 2014/0240038), and Saito et al. (US 6,731,007), Sakamoto et al. (US 2002/0030268), Iwasaki (US 6,128,173), and Deguchi et al. (US 2018/0374795), all of record, as applied to claim 9 above, and further in view of Fernandes et al. (US 5,310,626) of record.
(Re Claim 11) Modified Yoshino teaches the semiconductor device with a reference voltage circuit according to claim 9, but does not explicitly teach the semiconductor device wherein the impermeable film is amorphous silicon.
Fernandes teaches that amorphous silicon is a material that can be used to form a conductive layer (col. 6 ln. 1-6).
Modified Yoshino discloses the claimed invention except that a metal (Saito: col. 37 ln. 28-35) is used for an impermeable film instead of amorphous silicon. Fernandes shows that amorphous silicon is a functional equivalent in the art. Therefore, because these two materials were art-recognized alternatives at the time the invention was made, one of ordinary skill in the art would have found it obvious to substitute amorphous silicon for metal when forming an impermeable film. The use of a known material for its known properties is prima facie obvious. See MPEP 2143(B).
Response to Arguments
Applicant's arguments filed 12/12/2025 have been fully considered but they are not persuasive.
Applicant appears to argue that that the impermeable film “entirely separated from any lower wiring by the interlayer insulating film such that the impermeable film is electrically isolated from any conductive layer located below the interlayer insulating film” is supported by their drawings (p. 6). However, the drawings do not affirmatively demonstrate that the impermeable film is electrically isolated from any conductive layer located below the interlayer insulating film. The specification is silent about electrical isolation also. The specification even appears to allow for the electrical connection to conductive layers beneath the interlayer insulating film, as the impermeable film is described as part of the final wiring layer for multi-layer wiring (¶¶27-29). Nothing in the original disclosure confirms that the impermeable film is electrically isolated from any conductive layer located below the interlayer insulating film, and so the amended limitation as cited introduces new matter. See the 112(a) and 112(b) rejections above.
The remainder of Applicant’s arguments are moot.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898