DETAILED ACTION
This action is responsive to U.S. Patent Application No. 17/853,808 filed on 29 June 2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant's election with traverse of the Group I/A embodiment in the reply filed on 5 February 2026 is acknowledged. The traversal is on the ground(s) that:
As the above tables [comparing the claims to the figures] demonstrate, by way of example only, and not by way of limitation, definition, or exhaustion, claims 1 (asserted invention A) and 10 (asserted invention 10) read upon the same illustrated embodiment, overlap in scope, and are not mutually exclusive. The above tables further demonstrate that the Office has failed to establish that the asserted related processes are not capable of use together (which cannot be established as both processes read upon a common embodiment) or have materially different design, mode of operation, function, or effect (again, inconsistent with the evidence that both claim set read upon a same disclosed embodiment). Similar analysis applies to claims 2-8 and 10-17.
Applicant Arguments/Remarks Made in an Amendment (filed 10 March 2026) at 12. The Examiner respectfully disagrees.
“To support a requirement for restriction between two or more related product inventions, or between two or more related process inventions, both two-way distinctness and reasons for insisting on restriction are necessary, i.e., separate classification, status in the art, or field of search.” MPEP § 806.05(j). Regarding the overlap in scope prong, prong (A), the MPEP states: “the inventions as claimed do not overlap in scope, i.e., are mutually exclusive (i.e., a claim to the final product does not read on the intermediate, and vice versa) . . . .” Id. (emphasis in original).
While Applicant’s comparison of separate claims to the drawings is appreciated, the Examiner respectfully asserts that Applicant fails to compare the claims to each other as required by the analysis. Such claim comparison forms the basis for and supports the restriction requirement between the processes, and is provided in Table 1, below.
Claim 1
Claim 9
A method of forming a package device, the method including: forming a bottom die, the bottom die including bottom contact pads embedded within and having respective top surfaces level with a bottom dielectric bonding layer; forming a first top die by: forming a transistor structure on a bulk semiconductor substrate, forming a top interconnect structure on a top surface of the transistor structure; bonding the top interconnect structure to a first support substrate, removing the bulk semiconductor substrate from the transistor structure; forming a bottom interconnect structure on a bottom surface of the transistor structure; and directly bonding one of the top interconnect structure and the bottom interconnect structure onto the bottom die.
A method of forming a package device, the method comprising: forming a first top die by forming a transistor layer containing transistors in a front surface of a bulk substrate; forming a first interconnect structure on a front surface of the transistor layer by depositing on the front surface of the bulk substrate a stack conductive layers embedded within respective layers of a stack of deposited dielectric layers; bonding a first support substrate to a top surface of the first interconnect structure; thinning back a bottom surface of the bulk substrate to remove the bulk substrate from the transistor layer; forming a second interconnect structure on a second surface of the transistor layer, opposite the front surface of the transistor layer; forming a first bonding layer on a top surface of a structure selected from the group consisting of the first interconnect structure, the second interconnect structure, and both the first and the second interconnect structure, the first bonding layer including first bonding pads embedded within a first bonding dielectric layer; positioning the first top die over a bottom die having a bottom bonding layer including second bonding pads embedded within a second bonding dielectric layer; aligning respective first bonding pads to respective second bonding pads; and fusion bonding the first bonding layer to the second bonding layer and metal-to-metal bonding respective first bonding pads to respective second bonding pads; positioning a second top die over the bottom die and adjacent the first top die, the second top die having third bonding pads embedded within a third bonding dielectric layer; and fusion bonding the third bonding layer to the second bonding layer and metal-to-metal bonding respective third bonding pads to respective second bonding pads.
Table 1
As shown in Table 1, as a whole, the claims are completely different and encompass different steps and processes, such that there is no process that would infringe both of the identified inventions. Because the processes as claimed do not overlap in scope (i.e., are mutually exclusive), the inventions as claimed are not obvious variants according the current record, and the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect, all of which is addressed in the Restriction Requirement mailed 5 February 2026, Applicant’s arguments are unpersuasive.
The requirement is still deemed proper and is therefore made FINAL.
Claims 9-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Newly submitted claims 21-25 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
Claims 1-8, drawn to a method of making a package device, classified in H10W80/327.
Claims 9-15, drawn to a method of making a package device, classified in H10W80/331.
Claims 21-25, drawn to a method of making a package device, classified in H10W80/701.
Inventions A, B, and C are directed to related processes. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions as claimed are not capable of use together and are materially different. Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
the inventions have acquired a separate status in the art in view of their different classification; AND
the inventions require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries).
Accordingly, claims 21-25 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Publication No. 2022/0336393 (published Oct. 20, 2022) (hereinafter “Chen”).
Regarding independent claim 1, Chen discloses: A method of forming a package device (FIGS. 1-3, depicting a method of forming a semiconductor package, [0004]-[0006]), the method including:
forming a bottom die (FIGS. 3A-3D, wafer 102, [0048]), the bottom die including bottom contact pads embedded within and having respective top surfaces level with a bottom dielectric bonding layer (FIGS. 3A-3D, depicting wherein the wafer 102 includes die connectors 106 having top surfaces level with dielectric layer 104, [0052]);
forming a first top die (FIGS. 1/2A-F, substrate 12, [0023]) by:
forming a transistor structure on a bulk semiconductor substrate (FIG. 1, [0023]: “Devices may be formed at the active surface of the semiconductor substrate 12. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc.”),
forming a top interconnect structure on a top surface of the transistor structure (FIGS. 1/2A-F, interconnect structure 14A, [0033]);
bonding the top interconnect structure to a first support substrate (FIGS. 1/2A-F, depicting wherein the interconnect structure 14A is bonded to carrier substrate 52, [0043]),
removing the bulk semiconductor substrate from the transistor structure (FIGS. 1/2A-F, depicting wherein the substrate 12 is thinned, [0034]);
forming a bottom interconnect structure on a bottom surface of the transistor structure (FIGS. 1/2A-F, depicting wherein the memory cube includes various interconnect structures, including interconnect structure 14B, [0035]); and
directly bonding one of the top interconnect structure and the bottom interconnect structure onto the bottom die (FIGS. 1/2A-F/3A-D, depicting wherein the interconnect structure 14A is directly bonded to the wafter 102).
Regarding claim 2, Chen further discloses wherein the step of removing substantially all the bulk semiconductor substrate exposes a bottom surface of the transistor structure (FIGS. 1/2A-F, depicting wherein the step of thinning the substrate 12, wherein substantially all of the portion of the substrate 12 not including active devices is removed, and further wherein thinning exposes a bottom surface of the active device, e.g., conductive vias 16A, [0023], [0021]).
Regarding claim 3, Chen further discloses forming a transistor contact directly on the transistor structure (FIGS. 1/2A-F, e.g., conductive vias 16A); and wherein the step of forming a bottom interconnect structure includes forming a power rail in direct contact with the transistor contact (FIGS. 1/2A-F, depicting wherein the step of forming the interconnect structure 16B includes forming, e.g., connectors 22A/B and/or memory devices 11A-11H, which may be connected to power, [0047]).
Regarding claim 6, Chen further discloses forming aluminum landing pads in a top layer of the bottom interconnect structure (FIGS. 1/2A-F, depicting conductive vias 16 which may be formed from aluminum, [0025]) and forming copper bonding pads on the aluminum landing pads (FIGS. 1/2A-F, depicting die connectors 22 which may be formed from copper, [0027]).
Regarding claim 7, Chen further discloses wherein the step of directly bonding one of the top interconnect structure and the bottom interconnect structure onto the bottom die includes:
fusion bonding a top dielectric bonding layer of the first top die to the bottom dielectric bonding layer (FIGS. 1/2A-F/3A-D, [0053]: “Specifically, dielectric-to-dielectric bonds are formed between the dielectric layer 104 of the wafer 102 and the dielectric layer 24A of the memory cube 50”; [0039]: “The dielectric layer 58 is bonded to the dielectric layer 24B through dielectric-to-dielectric bonding, without using any adhesive material . . . . The bonding may include a pre-bonding and an annealing. . . . After the annealing, bonds, such as fusions bonds, are formed bonding the dielectric layer 24B and the dielectric layer 58.”), and
metal-to-metal bonding top bonding pads of the top die to the bottom contact pads of the bottom die ([0053]: “Specifically, dielectric-to-dielectric bonds are formed between the dielectric layer 104 of the wafer 102 and the dielectric layer 24A of the memory cube 50, and metal-to-metal bonds are formed between the die connectors 106 of the wafer 102 and the die connectors 22A of the memory cube 50.”).
Regarding claim 8, Chen further discloses wherein the step of removing the bulk semiconductor substrate from the transistor structure includes completely removing the bulk semiconductor substrate (FIGS. 1/2A-F, depicting wherein the step of thinning the substrate 12, wherein all of the portion of the substrate 12 not including active devices is removed).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of U.S. Patent Publication No. 2022/0045016 (published Feb. 10, 2022) (hereinafter “Jeng”).
Regarding claim 4, Chen further discloses wherein the top interconnect structure is directly bonded to the bottom interconnect structure (FIGS. 1/2A-F, depicting wherein the interconnect structure 14A is directly bonded to the interconnect structure 14B), and removing the first support substrate from the top interconnect structure (FIGS. 1/2A-F, depicting wherein the carrier substrate 52 is removed).
Chen does not specifically disclose bonding a second support substrate to the bottom interconnect structure.
In the same field of endeavor, Jeng discloses a method of forming a package device including bonding a support substrate to a bottom interconnect structure (FIGS. 1A-1J, [0027]: “FIGS. 1A-1J are cross-sectional views of various stages of a process for forming a package structure, in accordance with some embodiments. As shown in FIG. 1A, a carrier substrate 100 is provided or received.”). Regarding the carrier substrate, in [0027], Jeng states: “As shown in FIG. 1A, a carrier substrate 100 is provided or received. The carrier substrate 100 is used as a support substrate during the fabrication process. The carrier substrate 100 also functions as a reinforced plate that enhances the strength of the package structure, so as to prevent and/or reduce warpage of the package structure. The reliability and performance of the package structure are improved. In some embodiments, the carrier substrate 100 has a high strength and a low coefficient of thermal expansion (CTE).”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed method of forming a semiconductor package of Chen by adding a step of bonding a support substrate to a bottom interconnect structure as disclosed in Jeng in order to provide support during the fabrication process, enhance the strength of the package structure, and improve reliability and performance. See Jeng [0027].
Regarding claim 5, Chen in view of Jeng further discloses forming copper bonding pads in the top interconnect structure before the step of bonding the top interconnect structure to the first support substrate (FIG. 1, depicting wherein die connectors 22, which may be formed from copper are formed in the interconnect structure 14 prior to bonding to the carrier substrate 52, [0025]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Publication No. 2022/0093564 (published Mar. 24, 2022) (disclosing a package device similar to that of the instant disclosure).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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