DETAILED ACTION
The RCE filed December 02, 2025 has been entered. Claims 1-16 are pending. Claims 14-16 have been added. Claim 1 is independent.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “each memory cell of the plurality of memory cells including a cell frame”. There is not disclosure that a cell frame from the specification. So this language constitutes new matter.
Claims 2-16 are rejected due to claim dependency. Clarification is required.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-11, 13 and 16 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Nii (US 2011/0157965) in view of e.g., Vincent et al. (US 2021/0074350).
Regarding independent claim 1, as best as can be understood, Nii teaches a semiconductor memory device (e.g., FIG. 10 along with FIGS. 11-22), comprising:
first (FIG. 10: MCA top) and second (MCA second from top) memory sub-arrays arranged side by side in a first direction (vertical direction); and
a plurality of well tap cells (TC1 between top MCA and second from top MCA) arranged between the first and second memory arrays and arranged side by side in a second direction (horizontal direction) perpendicular to the first direction in plan view (see FIG. 10),
wherein the first and second memory sub-arrays each include
a plurality of memory cells arranged in an array (see FIG. 10), and
a first power rail (see FIG. 11: 6B (VDD1) which goes through MCA in FIG. 10) formed in a first interconnect layer, extending in the first direction (vertical direction), and configured to supply a first power supply voltage (VDD1) (see FIGS. 10-11 and accompanying disclosure, e.g., para. 0111: the memory cells MCA disposed … the wells … extending in …),
wherein the well tap cells include
a second power rail (FIG. 11: 6C (VDD1) which goes though TC1) formed in the first interconnect layer, extending in the first direction (vertical direction), electrically connected to the first power rail, and configured to supply the first power supply voltage (VDD1), and
a first line (FIG. 11: VDD) formed in a second interconnect layer that is above (see FIGS. 5 and 13, M3 above M2) the first interconnect layer, the first line extending in the second direction (horizontal direction), electrically connected to the second buried power rail, and configured to supply the first power supply voltage (VDD voltage domain), and
wherein the well tap cells supply a second power supply voltage to a well or the substrate in the memory cell (e.g., para. 0116: the tap cell TC1 causes the power source potential line VDD and the ground potential line VSS … VDD1, … VDD2 …).
Nii does not explicitly disclose the first interconnect layer being an interconnect layer below transistors formed in the memory cells.
However, the power rails (claimed the first interconnect layer) being located above or below memory transistors is a well-known technology for a type of memory layout for its purpose.
For support, of the above asserted facts, see for example, Vincent et al., e.g., FIG. 3: Layer 0, 332 VDD below Layer 1, 301, and accompanying disclosure.
Nii and Vincent are analogous art because they both are directed to SRAM memory device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Nii with the specified features of Vincent because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Vincent et al. to the teaching of Nii such that a memory, as taught by Nii, utilizes power rails, as taught by Vincent et al., for the purpose of utilizing power rails, thereby achieving compact memory design.
Nii and Vincent’ array do not explicitly disclose newly added claimed limitations of each memory cell of the plurality of memory cells including a cell frame; and the first power rail overlapping with a boundary between two adjacent memory cells of the plurality of memory cell.
However, the newly added claimed limitations are well-known technology in a memory array circuit and structure.
For support, of the above asserted facts, see for example, Lee et al. (US 2022/0037339), e.g., FIG. 5, Power rail, VDD and VSS overlapping with Cell Boundary, and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize power rail overlapping with a cell boundary for the purpose of area saving, and further these conventional technology are well established in the art of the memory devices.
Regarding claim 3, Nii and Vincent et al., as combined, teach the limitations of claim 1.
Nii further teaches the second power supply voltage is the same power supply voltage as the first power supply voltage (FIGS. 10-22: VDD1 and VDD2).
Regarding claim 4, Nii and Vincent et al., as combined, teach the limitations of claim 1.
Nii further teaches each of the well tap cells supplies the first power supply voltage to the well or the substrate in the memory cell, and supplies a third power supply voltage different from the first power supply voltage to the well or the substrate in the memory cell (FIGS. 10-22: VDD power domain and VSS power domain).
Regarding claims 5-6, Nii and Vincent et al., as combined, teach the limitations of claim 4.
Nii further teaches the well tap cells further include a second line formed in the line layer, extending in the second direction, and configured to supply the third power supply voltage; and the well tap cells further include a first region of a first conductive type, and a second region of a second conductive type different from the first conductive type, the well tap cells supply the first power supply voltage to the well or the substrate through the first region, and supplies the third power supply voltage to the well or the substrate through the second region (see FIGS. 10-22 and accompanying disclosure).
Regarding claim 7, Nii and Vincent et al., as combined, teach the limitations of claim 1.
Nii further teaches the first memory sub-array includes third and fourth memory sub-arrays where the plurality of memory cells are arranged in an array, the third and fourth memory sub-arrays being arranged side by side in the first direction, between the third and fourth memory sub-arrays, a plurality of BPR tap cells are arranged side by side in the second direction, and the BPR tap cells include a third buried power rail formed in the buried interconnect layer, extending in the first direction, electrically connected to the first buried power rail, and configured to supply the first power supply voltage, and a third line formed in the line layer, extending in the second direction, electrically connected to the second buried power rail, and configured to supply the first power supply voltage (see FIGS. 10-22 and accompanying disclosure).
Regarding claim 8, Nii and Vincent et al., as combined, teach the limitations of claim 1.
Nii further teaches the memory cells further include a fourth buried power rail formed in the buried interconnect layer, extending in the first direction, and configured to supply a third power supply voltage different from the first and the second power supply voltages, and the well tap cells further include a fifth buried power rail formed in the buried interconnect layer, extending in the first direction, electrically connected to the fourth buried power rail, and configured to supply the third power supply voltage, and a second line formed in the line layer, extending in the second direction, electrically connected to the fourth buried power rail, and configured to supply the third power supply voltage (see FIGS. 10-22 and accompanying disclosure).
Regarding claim 9, Nii and Vincent et al., as combined, teach the limitations of claim 1.
Nii further teaches the first memory sub-array includes third and fourth memory sub-arrays where the plurality of memory cells are arranged in an array, the third and fourth memory sub-arrays being arranged side by side in the first direction, between the third and fourth memory sub-arrays, a plurality of BPR tap cells are arranged side by side in the second direction, the memory cells further include a fourth buried power rail formed in the buried interconnect layer, extending in the first direction, and configured to supply a third power supply voltage different from the first and the second power supply voltages, and the BPR tap cells include a third buried power rail formed in the buried interconnect layer, extending in the first direction, electrically connected to the first buried power rail, and configured to supply the first power supply voltage, a third line formed in the line layer, extending in the second direction, electrically connected to the second buried power rail, and configured to supply the first power supply voltage, a sixth buried power rail formed in the buried interconnect layer, extending in the first direction, electrically connected to the fourth buried power rail, and configured to supply the third power supply voltage, and a fourth line formed in the line layer, extending in the second direction, electrically connected to the fourth buried power rail, and configured to supply the third power supply voltage (see FIGS. 10-22 and accompanying disclosure).
Regarding claim 10, Nii and Vincent et al., as combined, teach the limitations of claim 1.
Nii further teaches the second power supply voltage is a power supply voltage different from the first power supply voltage (FIGS. 10-22: VDD1 and VDD2).
Regarding claim 11, Nii and Vincent et al., as combined, teach the limitations of claim 10.
Nii further teaches the memory cells further include a fourth buried power rail formed in the buried interconnect layer, extending in the first direction, and configured to supply a third power supply voltage different from the first and the second power supply voltages, and the well tap cells further include a fifth buried power rail formed in the buried interconnect layer, extending in the first direction, electrically connected to the fourth buried power rail, and configured to supply the third power supply voltage, a second line formed in the line layer, extending in the second direction, electrically connected to the fourth buried power rail, and configured to supply the third power supply voltage, a fifth line formed in the line layer, extending in the second direction, and configured to supply the third power supply voltage, a first region of a first conductive type, and a second region of a second conductive type different from the first conductive type, the well tap cells supply the first power supply voltage to the well or the substrate through the first region, and supply the second power supply voltage to the well or the substrate through the second region (see FIGS. 10-22 and accompanying disclosure).
Regarding claim 13, Nii and Vincent et al., as combined, teach the limitations of claim 1.
Nii further teaches the second interconnect layer is an interconnect layer above the transistors. (FIG. 5).
Regarding claim 16, Nii and Vincent et al., as combined, teach the limitations of claim 1.
Nii further teaches a third power rail configured to supply a third power supply voltage is arranged in the first interconnect layer, and a fourth power rail configured to supply the third power supply voltage is arranged in the second interconnect layer (see e.g., FIGS. 2-5, 7, 11-19 and accompanying disclosure; further clamed power rail arrangement in a memory is a well-known technology in a memory device).
Allowable Subject Matter
Claims 2, 12 and 14-15 are rejected but would be allowable if overcoming 112(a) as indicated above rejection.
Conclusion
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/SUNG IL CHO/Primary Examiner, Art Unit 2825