CTNF 18/507,019 CTNF 91783 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of claims 1-13 in the reply filed on 4/20/2026 is acknowledged. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 1-3 and 10-13 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Parekh US 2021/0398847 . Re claim 1 , Parekh teaches a method of manufacturing a semiconductor device (200, fig7, [60]), the method comprising: providing a semiconductor substrate (206, 204, fig6A, 7, [27, 61]) configured for housing data storage cells (memory array in 204, fig7, [61]), wherein the provided semiconductor substrate includes (1) bit lines (102, fig1A, [28]) extending linearly and parallel to each other, (2) a cover layer (104, fig1A, [30]) over each of the bit lines, and (3) trenches (106, fig1A, [33]) separating adjacent pairs of the bit lines and extending below the bit lines (trench 106 reaches in a downward direction past the top surface of 102, fig1A); depositing a patterning layer (108, fig2A, [[34]) over a target bit line (102 under 112, fig2A and 3A), wherein the patterning layer has a mask opening (112, fig3A, [38]) for the target bit line at a target location (102 under 112, fig2A and 3A), the mask opening exposing (1) the cover layer (108, fig3A, [[34]) for the corresponding target bit line (102 under 112, fig2A and 3A) and (2) portions of the trenches (106 on each side of 102 under 112, fig3A) surrounding the target bit line at the target location; depositing a controlled amount of a conformal layer (114, fig4A, [42]) over the patterning layer (108, fig4A, [[34]) and within the mask opening (112, fig4A), wherein depositing the controlled amount of the conformal layer includes forming a conformal depression (114 in 112, fig4A) that is (1) directly over a portion of the corresponding target bit line (102 under 112, fig4A) within the mask opening (112, fig4A) and (2) concentrically arranged with the mask opening (112, fig4A and 4B), the portion of the corresponding target bit line (102, fig4A), or both; forming a contact opening (118, fig5A, [48]) at the target location using the conformal depression (114 in 112, fig4A), wherein forming the contact opening includes removing the cover layer (104, fig5A) to expose the target bit line (102 with 104 removed, fig5A) at the corresponding target location; and forming a vertical connector (120, fig6A, [50]) and a landing pad (124, fig6A, [50]) at the target location based on filling the contact opening with electrically conductive material ([50]), wherein the vertical contact (120, fig6A, [50]) is configured to provide a conductive path to the target bit line and includes an upper portion (part of 120 in contact with 116, fig6A, [51]) and a lower portion (part of 120 under 116, fig6A, [51]) that are concentrically arranged. Re claim 2 , Parekh teaches the method of claim 1, wherein depositing the controlled amount of the conformal layer (114, fig4A, [42]) to form the conformal depression (114 in 112, fig4A) and forming the vertical connector (120, fig6A, [50]) based on filling the contact opening comprise forming the vertical connector having the upper and lower portions that are self-aligned according to the concentric arrangement of the mask opening (T shaped 120 formed in opening 118, fig5A and 6A), a portion of the cover layer (104 around 120, fig6B, [30]), the portion of the target bit line (102 under 112, fig5B and 6B), or a combination thereof. Re claim 3 , Parekh teaches the method of claim 2, wherein: the mask opening has an opening width (width of 112, fig3A, [38]); and the controlled amount of the conformal layer corresponds to a thickness of the conformal layer (114, fig4A, [42]), wherein the thickness is less than the opening width (thickness of 114 less than width of 112, fig4A). Re claim 10 , Parekh teaches the method of claim 1, wherein the semiconductor device comprises a semiconductor wafer (204 and 206 above 122, fig7, [61]) including a memory array (204, fig7, [61]) having the data storage cells, wherein the memory array further includes the bit lines (102, fig7, [28]). Re claim 11 , Parekh teaches the method of claim 10, wherein the semiconductor wafer is a second semiconductor wafer (204 and 206 above 122, fig7, [61]), the method further comprising: bonding a first semiconductor wafer (202, fig7, [61]) over the second semiconductor wafer (204 and 206 above 122, fig7, [61]), wherein the first semiconductor wafer (202, fig7 and 8A, [61]) is connected to the landing pad (124 in 122, fig6A and 7, [50]) for electrically coupling to the target bit line (102, fig7, [28]). Re claim 12 , Parekh teaches the method of claim 11, wherein the first semiconductor wafer includes a control circuit (202, fig7 and 8A, [63]) that is coupled to the target bit line (102, fig7, [28]) and configured to access the target bit line through the self-aligned vertical connector (120, fig6A and 7, [50]). Re claim 13 , Parekh teaches the method of claim 12, wherein the first and second semiconductor wafers comprise a Flash memory device (200, fig7, [60]). Allowable Subject Matter 07-43 Claim 4-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim. Specifically, the limitations are material to the inventive concept of the application in hand to form a self-aligned contact on the target bit line. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOMING LIU whose telephone number is (571)270-0384. The examiner can normally be reached Monday-Friday, 9am-8pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /XIAOMING LIU/Examiner, Art Unit 2812 Application/Control Number: 18/507,019 Page 2 Art Unit: 2812 Application/Control Number: 18/507,019 Page 3 Art Unit: 2812 Application/Control Number: 18/507,019 Page 4 Art Unit: 2812 Application/Control Number: 18/507,019 Page 5 Art Unit: 2812 Application/Control Number: 18/507,019 Page 6 Art Unit: 2812
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