DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Specification
5. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
“Super-Junction MOSFET Switching Device”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 1-5, 7-12 and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Osawa, Yuto et al. (Pub No. US 20210098570 A1) (hereinafter, Osawa).
Osawa, Fig 5: Semiconductor device with super junction region
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Re Claim 1, Osawa teaches a semiconductor device comprising:
a first semiconductor layer (First column regions; 13; Fig 5; ¶[0033]) of a first conductivity type (N-type impurities; ¶[0033]);
at least one second semiconductor layer (Second column regions; 14; Fig 5; ¶[0033]) of a second conductivity type (P-type impurities; ¶[0033]) formed in the first semiconductor layer to have an annular shape (Column regions 14 form a ring/aperture shape in plan view; Fig 3) in a plan view (In the xy-plane; Fig 3); (See Fig 3 below)
Osawa, Fig 3: Plan-view of super junction MOSFET pad region
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an insulating layer (Region insulating layer/intermediate insulating layer; 51/66; Fig 5; ¶[0078]) formed on the first semiconductor layer;
a first metal layer (Equipotential electrode/source pad electrode; 85/83; Fig 5; ¶[0111]) and a second metal layer (Gate pad electrode; 81; Fig 5; ¶[0098]) formed on the insulating layer and spaced apart from each other;
a second wiring layer (Gate wiring layer/Portion of electrode 81 within insulating layer 66 directly above gate wiring layer 61; 61; Fig 5; ¶[0083]) provided in the insulating layer and configured to electrically connect an inner region (Located to the left and including 81; Fig 3; ¶¶[0083-0084]) of the first semiconductor layer surrounded by the at least one second semiconductor layer and the second metal layer; and
a first wiring layer (Equipotential wiring layer/Portion of equipotential electrode 85 within insulating layer 66 and directly above wiring layer 65; 65; Fig 5; ¶[0090]) provided in the insulating layer and configured to electrically connect an outer region (From the outer side surfaces to low resistance region 31; Fig 3; ¶[0091]) of the first semiconductor layer on the opposite side from the inner region with respect to the at least one second semiconductor layer and the first metal layer,
wherein the second metal layer overlaps with an entire inner region (Located within the annular loop to the left and including 81i, i.e. outside region 6; Figs 2/3; ¶[0083]) in the plan view,
wherein the second wiring layer is provided in the insulating layer at a position overlapping with the inner region to have an annular shape (Gate wiring layer 61 faces low resistance region 31 and is located in outside region 6, which is located within the annular loop to the left and including 81; ¶¶[0083-0084]) in the plan view,
wherein the outer region includes:
a first overlapping region (Region comprising of equipotential electrode 85; Fig 3) overlapping with the first metal layer in the plan view; and
a second overlapping region (Region comprising of gate pad electrode 81; Fig 3) overlapping with the second metal layer in the plan view,
wherein the first wiring layer includes:
a first main body portion (Equipotential wiring layer; 65; Fig 5; ¶[0091]) embedded in the insulating layer at a position (Spaced to the first to fourth side surfaces 5A to 5D side from low resistance region 31; Fig 2; ¶[0091]) overlapping with the outer region, formed in an annular shape (Belt shape; ¶[0091]) to surround the at least one second semiconductor layer, and electrically connected to the outer region; and (See Fig 2 below)
Osawa, Fig 2: Full plan-view of super junction MOSFET
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a first connection portion (Portion of equipotential electrode 85 within insulating layer 66 and directly above wiring layer 65; Fig 5) selectively provided in the insulating layer at a position overlapping with the first overlapping region and configured to electrically connect (Connects wiring layer 65 to upper equipotential electrode 85; Fig 5) the first main body portion and the first metal layer, and
wherein an annular diode (PN junction diode which contains second column region 14 and drift region 11, i.e. including first column region 13; ¶[0039]) constituted by the first semiconductor layer and the at least one second semiconductor layer is surrounded by the first main body portion and the second wiring layer, which are formed in the annular shape, in the plan view.
Re Claim 2, Osawa teaches the semiconductor device of Claim 1, wherein the second wiring layer (Gate wiring layer/Portion of electrode 81 within insulating layer 66 directly above gate wiring layer 61; 61; Fig 5; ¶[0083]) penetrates the insulating layer (Region insulating layer/intermediate insulating layer; 51/66; Fig 5; ¶[0078]) over an entire circumference thereof (Per ¶[0083] The gate wiring layer 61 is selectively drawn around on the region insulating layer 51) and electrically connects the second metal layer (Gate pad electrode; 81; Fig 5; ¶[0098]) and the inner region (Located within the annular loop to the left and including 81i, i.e. outside region 6; Figs 2/3; ¶[0083]).
Re Claim 3, Osawa teaches the semiconductor device of Claim 1, wherein the second wiring layer (Gate wiring layer/Portion of electrode 85 within insulating layer 66 directly above gate wiring layer 61; 61; Fig 5; ¶[0083]) includes:
a second main body portion (Gate wiring layer; 61; Fig 5; ¶[0083]) embedded in the insulating layer (Region insulating layer/intermediate insulating layer; 51/66; Fig 5; ¶[0078]) at a position overlapping with the inner region (Located to the left and including 81; Fig 3; ¶¶[0083-0084]) and electrically connected to the inner region; and
a second connection portion (Portion of electrode 81 within insulating layer 66 directly above gate wiring layer 61; Fig 5; ¶[0083]) provided in the insulating layer so as to overlap (81 overlaps 61; Fig 5) with the second main body portion and configured to electrically connect the second main body portion and the second metal layer (Gate pad electrode; 81; Fig 5; ¶[0098]).
Re Claim 4, Osawa teaches the semiconductor device of Claim 1, wherein the at least one second semiconductor layer (Second column regions; 14; Fig 5; ¶[0033]) includes a plurality of second semiconductor layers (Second column regions 14 include a plurality of second column regions; Fig 5).
Re Claim 5, Osawa teaches the semiconductor device of Claim 1, wherein the insulating layer (Region insulating layer/intermediate insulating layer; 51/66; Fig 5; ¶[0078]) includes a first insulating layer (Region insulating layer; 51; Fig 5; ¶[0078]) configured to cover the first semiconductor layer (First column regions; 13; Fig 5; ¶[0033]), and a second insulating layer (Intermediate insulating layer; 51/66; Fig 5; ¶[0078]) configured to cover the first insulating layer.
Re Claim 7, Osawa teaches the semiconductor device of Claim 1, wherein the at least one second semiconductor layer (Second column regions; 14; Fig 5; ¶[0033]) is formed in a rectangular annular shape (Belt shape; ¶[0037]), and
wherein the first overlapping region (Region comprising of equipotential electrode 83; Fig 3) overlaps with two adjacent straight portions (Equipotential electrode 83 overlaps the second column regions 14 in the y-direction; Fig 3) of the at least one second semiconductor layer.
Re Claim 8, Osawa teaches the semiconductor device of Claim 7, wherein the first connection portion (Portion of equipotential electrode 85 within insulating layer 66 and directly above wiring layer 65; Fig 5) is formed along two sides (At least two side surfaces 5A to 5D (not illustrated); ¶[0111]) adjacent to the first metal layer (Equipotential electrode/source pad electrode; 85/83; Fig 5; ¶[0111]) in the plan view.
Re Claim 9, Osawa teaches the semiconductor device of Claim 1, wherein the at least one second semiconductor layer (Second column regions; 14; Fig 5; ¶[0033]) is formed in a rectangular annular shape (Belt shape; ¶[0037]), and
wherein the first overlapping region (Region comprising of equipotential electrode 83; Fig 3) overlaps with three straight portions (Equipotential electrode 83 overlaps the three straight portions of second column regions 14 in the y-direction; Fig 3) of the at least one second semiconductor layer.
Re Claim 10, Osawa teaches the semiconductor device of Claim 9, wherein the first connection portion (Portion of equipotential electrode 85 within insulating layer 66 and directly above wiring layer 65; Fig 5) is formed along three sides (At least two side surfaces 5A to 5D (not illustrated); ¶[0111]) adjacent to the first metal layer (Equipotential electrode/source pad electrode; 85/83; Fig 5; ¶[0111]) in the plan view.
Re Claim 11, Osawa teaches the semiconductor device of Claim 1, wherein the first connection portion (Portion of equipotential electrode 85 within insulating layer 66 and directly above wiring layer 65; Fig 5) is not formed in a portion corresponding to a gap (The gap between 85 and 81 in the y-direction; Fig 5) between the second metal layer (Gate pad electrode; 81; Fig 5; ¶[0098]) and the first metal layer (Equipotential electrode/source pad electrode; 85/83; Fig 5; ¶[0111]).
Re Claim 12, Osawa teaches the semiconductor device of Claim 1, wherein an end of the first connection portion (Portion of equipotential electrode 85 within insulating layer 66 and directly above wiring layer 65; Fig 5) is arranged on the inner side (Within outside region 6; Figs 2/3; Note: Fig 3 is a close-up of outside region 6 and surrounding regions of Fig 2) of the first overlapping region than an end (Outside of the outside region 6; Figs 2/3) of the first overlapping region (Region comprising of equipotential electrode 83; Fig 3.
Re Claim 16, Osawa teaches the semiconductor device of Claim 1, further comprising:
a semiconductor layer (P-type FL region/low resistance region; 21/31; Figs 5/8; ¶[0044]; Note: Fig 8 is a continuation from Fig 5 comprising of the low resistance region 31, according to the plan-view illustration of Fig 3); and
an insulating layer (Region insulating layer/intermediate insulating layer; 51/66; Fig 5; ¶[0078]) formed on (Region insulating layer 51 is in contact with P-type FL region 21; Fig 5) the semiconductor layer,
wherein the first semiconductor layer (First column regions; 13; Fig 5; ¶[0033]) and the at least one second semiconductor layer (Second column regions; 14; Fig 5; ¶[0033]) are formed on (First and second column regions 13/14 in contact with region insulating layer 51 on left side; Fig 5) the insulating layer.
Osawa, Fig 8: Close-up view of main part of Fig 5
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Re Claim 17, Osawa teaches the semiconductor device of Claim 16, wherein the semiconductor layer (P-type FL region/low resistance region; 21/31; Figs 5/8; ¶[0044]; Note: Fig 8 is a continuation from Fig 5 comprising of the low resistance region 31, according to the plan-view illustration of Fig 3) includes a diffusion layer (N-type source regions; 46; Fig 8; ¶[0070]) of the first conductivity type (N-type conductivity; ¶[0070]) provided in a cell region (Cell Region; 7; Figs 5/8; ¶[0025]; Note: Fig 8 is an enlarged portion of cell region 7 from Fig 5) of the semiconductor layer overlapping with the first metal layer (Equipotential electrode/source pad electrode; 85/83; Fig 5; ¶[0111]) in the plan view (Fig 3), and
wherein the first metal layer is electrically connected to the diffusion layer by a first via (Gate electrode; 45; Fig 8; ¶[0069]) arranged at a position (Overlapping cell region 7; Fig 8) overlapping with the cell region in the plan view.
Re Claim 18, Osawa teaches the semiconductor device of Claim 17, wherein the first via (Gate electrode; 45; Fig 8; ¶[0069]) is made of the same material (Polysilicon; ¶¶[0069, 0083]) as the second wiring layer (Gate wiring layer/Portion of electrode 85 within insulating layer 66 directly above gate wiring layer 61; 61; Fig 5; ¶[0083]) and the first wiring layer (Equipotential wiring layer/Portion of equipotential electrode 85 within insulating layer 66 and directly above wiring layer 65; 65; Fig 5; ¶[0090]).
Re Claim 19, Osawa teaches a semiconductor device comprising:
a first semiconductor layer (First column regions; 13; Fig 5; ¶[0033]) of a first conductivity type (N-type impurities; ¶[0033]);
at least one second semiconductor layer (Second column regions; 14; Fig 5; ¶[0033]) of a second conductivity type (P-type impurities; ¶[0033]) provided in the first semiconductor layer and configured to divide the first semiconductor layer into a first region (Left side of leftmost second column layer 14; Fig 5) and a second region (Cell region; 7; Figs 5/8; ¶[0084]; Note: Fig 8 is a close-up of cell region 7) on the opposite side of the first region;
a first insulating layer (Region insulating layer; 51; Fig 5; ¶[0078]) formed on the first semiconductor layer;
a second insulating layer (Intermediate insulating layer; 66; Fig 5; ¶[0078]) formed on the first insulating layer;
a first metal layer (Equipotential electrode; 85; Fig 5; ¶[0111]) and a second metal layer (Gate pad electrode/source pad electrode; 81/83; Fig 5; ¶[0098]) formed on the second insulating layer and spaced apart from each other;
a first wiring layer (Equipotential wiring layer/Portion of equipotential electrode 85 within insulating layer 66 and directly above wiring layer 65; 65; Fig 5; ¶[0090]) configured to electrically connect the first region and the first metal layer; and
a second wiring layer (Gate wiring layer/Portion of electrode 81 within insulating layer 66 directly above gate wiring layer 61; 61; Fig 5; ¶[0083]) configured to electrically connect the second region and the second metal layer,
wherein the second metal layer overlaps with an entire second region in a plan view (Source pad electrode 83 overlaps the cell region 7 in the plan view; ¶[0106]),
wherein the first region includes:
a first overlapping region (Region comprising of equipotential electrode 85; Fig 3) overlapping with the first metal layer in the plan view; and
a second overlapping region (Region comprising of gate pad electrode 81; Fig 3) overlapping with the second metal layer in the plan view,
wherein the first wiring layer includes:
a first main body portion (Equipotential wiring layer; 65; Fig 5; ¶[0091]) embedded in the first insulating layer at a position (Spaced to the first to fourth side surfaces 5A to 5D side from low resistance region 31; Fig 2; ¶[0091]) overlapping with the first region; and
a first connection portion (Portion of equipotential electrode 85 within insulating layer 66 and directly above wiring layer 65; Fig 5) selectively provided in the second insulating layer at a position (The equipotential electrode 85 is formed with a space from the low resistance region 31 to the first to fourth side surfaces 5A to 5D side in plan view; ¶[0112]) overlapping with the first overlapping region and configured to electrically connect (Connects wiring layer 65 to upper equipotential electrode 85; Fig 5) the first main body portion and the first metal layer.
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Osawa, Yuto et al. (Pub No. US 20210098570 A1) (hereinafter, Osawa) as applied to claim 5 above, and further in view of Hikasa, Akihiro et al. (Pub No. US 20150060937 A1) (hereinafter, Hikasa).
Re Claim 6, Osawa teaches the semiconductor device of Claim 5, wherein the first connection portion (Portion of equipotential electrode 85 within insulating layer 66 and directly above wiring layer 65; Fig 5) is provided in the second insulating layer (Intermediate insulating layer; 51/66; Fig 5; ¶[0078]).
However, Osawa does not teach wherein the first main body portion is provided in the first insulating layer.
In the same field of endeavor, Hikasa teaches wherein the first main body portion (Emitter electrode portion inside insulating film 18; 6; Fig 2A; ¶[0114]) is provided in the first insulating layer (Insulating film; 18; Fig 2A; ¶[0107]). (See Fig 2A below)
Hikasa, Fig 2A: Semiconductor device with IGBT elements, comprising of a first main body portion provided inside of insulating layer
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the first main body portion which is provided in the first insulating layer, as taught by Hikasa, with the semiconductor device as taught by Osawa. One would have been motivated to do this with a reasonable expectation of success in order to have the emitter electrode is embedded between the insulating films, such that the emitter electrode may be electrically isolated between the control terminal and the emitter/collector.
10. Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Osawa, Yuto et al. (Pub No. US 20210098570 A1) (hereinafter, Osawa) as applied to claim 12 above, and further in view of Hirler, Franz et al. (Pub No. US 20170373140 A1) (hereinafter, Hirler).
Re Claim 13, Osawa does not teach the semiconductor device of Claim 12, wherein the at least one second semiconductor layer includes four straight portions and four arc-shaped corner portions respectively provided between two adjacent straight portions.
In the same field of endeavor, Hirler teaches the semiconductor device of Claim 12, wherein the at least one second semiconductor layer (Second zones; 182; Fig 3; ¶[0062]) includes four straight portions (Second zones 182 may be rectangular in the active area 610; Figs 2G/3; ¶[0062]) and four arc-shaped corner portions (Second zones 182 may be rectangular with rounded corners in active area 610; Figs 2G/3; ¶[0062]) respectively provided between two adjacent straight portions (Straight portions surrounding active area 610 between corners; Fig 2G). (See Figs 2G/3 below)
Hirler, Figs 2G: Plan-view of super junction IGFET
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Hirler, Fig 3: Cross-section of super junction IGFET
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the at least one second semiconductor layer includes four straight portions and four arc-shaped corner portions respectively provided between two adjacent straight portions, as taught by Hirler, with the semiconductor device as taught by Osawa. One would have been motivated to do this with a reasonable expectation of success because the symmetry of the second semiconductor layers allows for a higher breakdown voltage within the drift region, as well as lower on-resistance in order to improve power efficiency.
Re Claim 14, Osawa teaches the semiconductor device of Claim 13, wherein the first main body portion (Equipotential wiring layer; 65; Fig 5; ¶[0091]) is formed in an arc shape (Belt shape; i.e. comprises arc-shape on corners; ¶[0091]) in conformity with the corner portions (Corner portions where low resistance region 31 intersects with second column region 14; Fig 3; ¶[0091]) of the at least one second semiconductor layer (Second column regions; 14; Fig 5; ¶[0033]).
Re Claim 15, Osawa teaches the semiconductor device of Claim 13, wherein the first connection portion (Portion of equipotential electrode 85 within insulating layer 66 and directly above wiring layer 65; Fig 5) is provided only in the straight portions (Outside/to the right of low resistance region 31 where second column regions 14 are straight; Fig 3) of the at least one second semiconductor layer (Second column regions; 14; Fig 5; ¶[0033]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Hsieh, Fu-Yuan et al. (Pub No. US 20100314681 A1) discloses a structure of power semiconductor device integrated with clamp diodes sharing same gate metal pad is disclosed. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon.
[2] Nasu, Kentaro et al. (Pub No. CN 112786591 B) discloses the present invention provides a semiconductor device, which comprises: an enhanced first p-channel type MISFET; an enhanced second p-channel type MISFET; a drain conductor electrically connected to drain electrodes of the first p-channel type MISFET and the second p-channel type MISFET; a first source conductor electrically connected to a source of the first p-channel MISFET; a second source conductor electrically connected to the source of the second p-channel MISFET; and a gate conductor electrically connected to the gate common ground of the first p-channel MISFET and the second p-channel MISFET. Thus, the semiconductor device capable of realizing miniaturization of element of normal conduction type can be provided.
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817
/T.E.D./
Examiner
Art Unit 2817