Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
“Two-dimensionally Active Regions Separated By Device isolations Including Word Lines and Bit Lines”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 10, 14 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (US 2019/0164975 A1) in view of and Choi et al. (US 2017/0076974 A1) and Kim et al. (US 2019/0206877 A1).
Regarding independent claim 1: Song teaches (e.g., Figs. 1A-1C) a semiconductor device, comprising:
a substrate ([0021]: 100);
a device isolation part ([0021]: 102) on the substrate and defining active regions ([0021]: ACT) that are two-dimensionally disposed in a first direction and a second direction (Figs. 1A-1B),
the active regions each extending in the first direction (vertical direction);
first word lines ([0022]: WL) crossing the active regions in the second direction (horizontal direction);
a first impurity region ([0028]: 112a) in an active region between the first word lines;
a second impurity region ([0023]: 112b) in an active region at one side of the first word line (WL) and spaced apart from the first impurity region (112a);
a bit line ([0027]-[0028]: BL);
at least one storage node contact structure ([0030]: BC);
a landing pad ([0031]-[0032]: LP) on the at least one storage node contact structure (BC).
Song does not expressly teach
second word lines adjacent to first word lines in the first direction;
at least one first conductive pad in contact with the first impurity region;
at least one second conductive pad in contact with the second impurity region;
a bit line on the at least one first conductive pad and extending in the first direction;
at least one storage node contact structure on the at least one second conductive pad.
Choi teaches (e.g., Fig. 19 and Figs. 31A-33; using other Figure for purpose of description; the same elements labels must be consistent with nomenclature, per MPEP) a semiconductor device, comprising:
a substrate ([0073]: 100);
at least one first conductive pad ([0129]: 130) in contact with the first impurity region ([0220]: 112a);
at least one second conductive pad ([0080] and [0202]: 120) in contact with the second impurity region ([0199]: 112b);
a bit line ([0084] and [0165]: 135) on the at least one first conductive pad and extending in the first direction (vertical direction);
at least one storage node contact structure ([0154]: 210a) on the at least one second conductive pad (120); and
a landing pad ([0160]: 240L) on the at least one storage node contact structure (240a).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Song, the at least one first conductive pad in contact with the first impurity region; at least one second conductive pad in contact with the second impurity region; a bit line on the at least one first conductive pad and extending in the first direction; at least one storage node contact structure on the at least one second conductive pad; and a landing pad on the at least one storage node contact structure, as taught by Choi, for the benefits of reducing the contact resistance of the active regions interconnections to the storage node, and thus improve device operation speed.
Kim teaches (e.g., Fig. 3C) a semiconductor device, comprising second word lines ([0075]: WL(UE)) adjacent to first word line ([0075]: WL(BE)) in a first direction (vertical direction).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Song as modified by Choi, the second word lines adjacent to first word lines in the first direction, as taught by Kim, for the benefits of avoiding open-circuit in the word lines, by providing a stack of word lines; additionally, it allows for threshold voltage modulation based on electrical characteristics needed.
Regarding claim 2: Song, Choi and Kim teach the claim limitation of the semiconductor device as claimed in claim 1, on which this claim depends,
Song as modified by Choi and Kim teaches that one of the active regions (Song: ACT) includes a first sidewall and a second sidewall that are opposite to each other (left side and right sides or ACT) and extend in the first direction (vertical direction),
the bit line (Choi: Fig. 31A; [0084] and [0165]: 135), the at least one first conductive pad (Choi: 130), and the at least one second conductive pad (Choi: 120) overlap the first sidewall and are spaced apart from the second sidewall when viewed in a plan view (Choi: Fig. 31A), and
the at least one storage node contact structure (Choi: 210a) overlaps the second sidewall and is spaced apart from the first sidewall when viewed in a plan view (Choi: Fig. 31A).
Regarding claim 3: Song, Choi and Kim teach the claim limitation of the semiconductor device as claimed in claim 1, on which this claim depends,
wherein: the active regions includes a first active region, a second active region, a third active region, and a fourth active region (Song: Figs. 1A-1B; from left to right, regions ACT) which are arranged in a clockwise direction (Song: Figs. 1A-1B), and
the device isolation part includes:
a first device isolation part (Song: 102, left most part) between the first active region and the second active region of the active regions and extending in the first direction (Song: vertical direction); and
a second device isolation part (Song: 102, second from left most part) between the first active region and the fourth active region of the active regions (Song: Figs. 1A-1B; from left to right, regions ACT) and between the second active region and the third active region of the active regions (Song: Figs. 1A-1B; from left to right, regions ACT) and extending in the second direction (Song: horizontal direction).
Regarding claim 10: Song, Choi and Kim teach the claim limitation of the semiconductor device as claimed in claim 1, on which this claim depends.
Song as modified by Choi and Kim teaches a gate insulating layer (Song: [0042]: 107) between the first word line (Song: WL) and the substrate (Song: 100),
wherein the at least one second conductive pad (Kim: WL(UE)) overlaps the gate insulating layer, and
wherein the storage node contact structure (Song: [0030]: BC) overlaps the first word line (Song: WL).
Regarding claim 14: Song, Choi and Kim teach the claim limitation of the semiconductor device as claimed in claim 1, on which this claim depends,
Song as modified by Choi and Kim teaches that
the device isolation part (Song: 102) is lower than an upper surface of the substrate (Song: 100) and exposes a side surface of the substrate, and
the at least one first conductive pad (Choi: 130) and the at least one second conductive pad (Choi: 120) are each in contact with the side surface of the substrate (Choi: 100).
Regarding claim 16: Song, Choi and Kim teach the claim limitation of the semiconductor device as claimed in claim 1, on which this claim depends,
Song as modified by Choi and Kim teaches that the active regions include a first active region and a second active region adjacent to each other in the second direction (Song: Fig. 1B; from left most to right side, active regions ACT), and
a first distance between a first impurity region (Song: left most side 112a) in the first active region and a second impurity region (Song: right side 112b) in the second active region is greater than a second distance between the first impurity region (Song: left most side 112a) in the first active region and a first impurity region (Song: second from left most side 112a) in the second active region (Song: second active region ACT from left side).
Regarding independent claim 17: Song teaches (e.g., Figs. 1A-1C) a semiconductor device, comprising:
a substrate ([0021]: 100);
a device isolation part ([0021]: 102) on the substrate and defining active regions ([0021]: ACT) that are two-dimensionally disposed in a first direction and a second direction (Figs. 1A-1B),
the active regions each extending in the first direction (vertical direction);
first word lines ([0022]: WL) crossing the active regions in the second direction (horizontal direction);
a first impurity region ([0028]: 112a) in an active region between the first word lines;
a second impurity region ([0023]: 112b) in an active region ([0021]: next active region ACT) at one side of the first word line and spaced apart from the first impurity region;
at least one first conductive pad in contact with the first impurity region;
at least one second conductive pad in contact with the second impurity region;
a bit line ([0027]-[0028]: BL); extending in the first direction (vertical direction); and
a storage node contact structure ([0030]: BC),
wherein: one of the active regions (ACT) includes a first sidewall and a second sidewall (left sidewall and right sidewall and of active region ACT) that are opposite to each other, extend in the first direction (vertical direction), and are parallel to each other,
the storage node contact structure (BC) overlaps the second sidewall (second sidewall of ACT) and is spaced apart from the first sidewall (first of sidewall ACT) when viewed in a plan view.
Song does not expressly teach
at least one first conductive pad in contact with the first impurity region;
at least one second conductive pad in contact with the second impurity region;
a bit line on the at least one first conductive pad and extending in the first direction; and
the bit line, the at least one first conductive pad, and the at least one second conductive pad overlap the first sidewall and are spaced apart from the second sidewall, when viewed in a plan view.
Choi teaches (e.g., Fig. 19 and Figs. 31A-33; using other Figure for purpose of description; the same elements labels must be consistent with nomenclature, per MPEP) a semiconductor device, comprising:
a substrate ([0073]: 100);
at least one first conductive pad ([0129]: 130) in contact with the first impurity region ([0220]: 112a);
at least one second conductive pad ([0080] and [0202]: 120) in contact with the second impurity region ([0199]: 112b);
a bit line ([0084] and [0165]: 135) on the at least one first conductive pad and extending in the first direction (vertical direction);
at least one storage node contact structure ([0154]: 210a) on the at least one second conductive pad (120); and
a landing pad ([0160]: 240L) on the at least one storage node contact structure (240a);
the bit line (135), the at least one first conductive pad (130), and the at least one second conductive pad (120) overlap the first sidewall (left sidewall of ACT) and are spaced apart from the second sidewall (right side sidewall of ACT), when viewed in a plan view.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Song, the at least one first conductive pad in contact with the first impurity region; at least one second conductive pad in contact with the second impurity region; a bit line on the at least one first conductive pad and extending in the first direction; at least one storage node contact structure on the at least one second conductive pad; and a landing pad on the at least one storage node contact structure; the bit line, the at least one first conductive pad, and the at least one second conductive pad overlap the first sidewall and are spaced apart from the second sidewall, when viewed in a plan view, as taught by Choi, for the benefits of reducing the contact resistance of the active regions interconnections to the storage node, and thus improve device operation speed and at the same time reduce the device footprint.
Kim teaches (e.g., Fig. 3C) a semiconductor device, comprising second word lines ([0075]: WL(UE)) adjacent to first word line ([0075]: WL(BE)) in a first direction (vertical direction).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Song as modified by Choi, the second word lines adjacent to first word lines in the first direction, as taught by Kim, for the benefits of avoiding open-circuit in the word lines, by providing a stack of word lines; additionally, it allows for threshold voltage modulation based on electrical characteristics needed.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (US 2019/0164975 A1) in view of and Choi et al. (US 2017/0076974 A1) and Kim et al. (US 2019/0206877 A1) as applied above and further in view of Miyajima et al. (US 2010/0176486 A1).
Regarding claim 15: Song, Choi and Kim teach the claim limitation of the semiconductor device as claimed in claim 1, on which this claim depends,
Song as modified by Choi and Kim does not expressly teach that a level of a lower end of the at least one first conductive pad is the same as a level of a lower end of the at least one second conductive pad.
Miyajima teaches (e.g., Fig. 4A) a semiconductor device comprising
a level of a lower end of at least one first conductive pad ([0059]-[0061]: left side pad 9) is the same as a level of a lower end of at least one second conductive pad ([0059]-[0061]: right side pad 9).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Song as modified by Choi and Kim, the first conductive pad and second conductive pad, wherein the level of the lower end of the at least one first conductive pad being the same as a level of a lower end of the at least one second conductive pad, as taught by Miyajima, for the benefits of reducing the overall thickness of the integrated circuit by making all pads being at the same level rather than stacked.
Allowable Subject Matter
Claims 4-9, 11-13 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a semiconductor device comprising:
“further comprising a dummy word line in the second device isolation part, wherein the dummy word line is electrically grounded or floated”.
Regarding claim 5: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a semiconductor device comprising:
“wherein the at least one storage node contact structure includes:
a first contact contacting the at least one second conductive pad and having a first width; and
a second contact on the first contact and having a second width greater than the first width”.
Claims 6-9 depend from claim 5, and therefore, are allowable for the same reason as claim 5.
Regarding claim 11: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a semiconductor device comprising:
“a third sidewall connecting the first sidewall and the second sidewall, and the first sidewall and the third sidewall meet at a first corner, the second sidewall and the third sidewall meet at a second corner, and each of the first corner and the second corner has an angle of 85 to 95 degrees”.
Regarding claim 12: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a semiconductor device comprising:
“wherein the at least one first conductive pad or the at least one second conductive pad includes: a first silicon pattern in contact with the substrate; and
a first ohmic pattern on the first silicon pattern”.
Regarding claim 13: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a semiconductor device comprising:
“wherein the bit line contact has a first width in the first direction, and wherein the at least one first conductive pad has a second width smaller than the first width in the first direction”.
Regarding claim 18: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a semiconductor device comprising:
“a second contact disposed on the first contact and having a second width greater than the first width, the at least one first conductive pad includes a plurality of first conductive pads, the at least one second conductive pad includes a plurality of second conductive pads,
the semiconductor device further includes: a first pad separation pattern between the plurality of first conductive pads and the plurality of second conductive pads in the first direction; and a second pad separation pattern between the plurality of second conductive pads in the second direction, an upper surface of the second pad separation pattern is flat, and the first contact includes a protruding portion covering upper and side surfaces of the second pad separation pattern and inserted into the plurality of second conductive pads”.
Claims 19-20 are allowable.
Regarding claim 19: the most relevant prior art references (e.g., Figs. Figs. 1A-1C of (US 2019/0164975 A1) to Song et al., e.g., Fig. 19 and Figs. 31A-33 of (US 2017/0076974 A1) to Choi et al. and e.g., Fig. 3C of (US 2019/0206877 A1) to Kim et al.), substantially teach the semiconductor device, comprising:
a substrate;
a device isolation part on the substrate and defining active regions that are two-dimensionally disposed in a first direction and a second direction, the active regions each extending in the first direction;
first and second word lines crossing the active regions in the second direction and adjacent to each other in the first direction;
a gate insulating layer between the first word line and the substrate;
a first impurity region in an active region between the first and second word lines;
a second impurity region in an active region at one side of the first word line and spaced apart from the first impurity region;
a first conductive pad in contact with the first impurity region;
a second conductive pad in contact with the second impurity region;
a bit line on the first conductive pad and extending in the first direction;
a storage node contact structure on the second conductive pad;
a landing pad on the storage node contact structure; and
However, none of the prior art references either singly or in proper combination discloses or fairly suggests, along with the other claimed features, a semiconductor device comprising:
“a word line capping pattern on each of the first and second word lines and buried in the substrate;
a first bit line spacer and a second bit line spacer sequentially between the bit line and the storage node contact structure,
wherein the active regions include a first active region and a second active region adjacent to each other in the second direction, and
wherein a first distance between a first impurity region in the first active region and a second impurity region in the second active region is greater than a second distance between the first impurity region in the first active region and a first impurity region in the second active region”.
Claim 20 depends from claim 19, and therefore, is allowable for the same reason as claim 19.
Conclusion
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/HERVE-LOUIS Y ASSOUMAN/Examiner, Art Unit 2812