DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 11/13/2023 is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Note applicable to all claims being rejected in this Office action: Examiner notes that the limitations "overlap", "layer", "portion" “on” “cover” “disposed” are being interpreted broadly in accordance with MPEP. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. The claim presently disclose s a structural limitation (i.e. overlap, layer, portion, contact) that is taught by prior art of record, therefore, the limitation is considered met by the prior art of record. Additionally, Merriam Webster dictionary defines the above limitations as “to occupy the same area in part”, “one thickness lying over or under another”, “an often limited part of a whole” “ used as a function word to indicate position in close proximity with ” “ to lay something over ” “arranged” respectively. Further note the limitation “contact” is being interpreted to include "direct contact" (no intermediate materials, elements or space disposed there between) and "indirect contact" (intermediate materials, elements or space disposed there between). Claim(s) 1-9, 11-18, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al (US 2021/0167050 A1 hereinafter Cho) . Regarding Claim 1, Cho discloses in Fig 2: A display device comprising: a pixel electrode (211 in via opening 319_1) disposed on a substrate (110) ; a bank layer (410) disposed on the substrate and the pixel electrode and separating an emission area from a non-emission area (See Fig 2) ; light emitting elements (300) each arranged on the pixel electrode and comprising a first semiconductor layer (310) , a second semiconductor layer (320) , and an active layer (330) disposed between the first semiconductor layer and the second semiconductor layer; a first capping layer (212) disposed on the pixel electrode and surrounding side surfaces of the light emitting elements [0107 : Cho discloses multiple stacks of electrode layers 212 and 211 ] ; a first reflective layer (211) disposed on the first capping layer and surrounding the side surfaces of the light emitting elements; a first via layer ( 261 ) disposed on the first reflective layer; a second via (530) layer disposed on the first via layer; and a common electrode ( 220 ) disposed on the second via layer and the light emitting elements. See notes above for broadest reasonable interpretation of “on”, “disposed” [0075, 0089, 0110-0120]. Regarding Claim 2 , Cho discloses in Fig 2: The display device of claim 1, wherein each of the light emitting elements (300) further comprises an insulating layer (380) surrounding side surfaces of the first semiconductor layer (310) , the active layer (330) , and the second semiconductor layer (320) , and the first capping layer (212) contacts (indirectly) the insulating layer (380) . Regarding Claim 3 , Cho discloses in Fig 2: The display device of claim 1, wherein the first reflective layer (211) is spaced apart from the light emitting elements (300) and contacts a surface of the first capping layer (212) . Regarding Claim 4 , Cho discloses in Fig 2: The display device of claim 1, wherein the first semiconductor layer (310) is disposed adjacent to the pixel electrode (211) , and the first capping layer (212) and the first reflective layer (211) surround (partially) a side surface of the first semiconductor layer (310) , a side surface of the active lay e r (330) , and a side surface of the second semiconductor layer (320) . Regarding Claim 5 , Cho discloses in Fig 2: The display device of claim 4, wherein the first capping layer (212) and the first reflective layer (211) surround at least a portion of the side surface of the second semiconductor layer (320) . Regarding Claim 6 , Cho discloses in Fig 2: The display device of claim 1, wherein a height of each of the first capping layer (212) and the first reflective layer (211) is less than heights of the light emitting elements (300) . Regarding Claim 7 , Cho discloses in Fig 2: The display device of claim 1, wherein a height of the first capping layer (212) and a height of the first reflective layer (211) are same. Regarding Claim 8 , Cho discloses in Fig 2: The display device of claim 1, wherein the first capping layer (212) and the first reflective layer (211) in the emission area are spaced apart from another first capping layer and another first reflective layer in an adjacent emission area (next pixel) and overlap the emission area in a plan view (See Fig 2) . Regarding Claim 9 , Cho discloses in Fig 2: The display device of claim 1, wherein the first via layer (261) contacts (indirectly) a top surface of the first reflective layer (211) , and is spaced apart from an edge of the first reflective layer (211) , and the second via layer covers the first via layer, the first reflective layer, and the first capping layer (See note above for the broadest reasonable interpretation of “cover”) . Regarding Claim 11 , Cho discloses in Fig 2: A display device comprising: a pixel electrode (211 in via opening 319_1) disposed on a substrate (110); a bank layer (410) disposed on the substrate and the pixel electrode and separating an emission area from a non-emission area (See Fig 2); light emitting elements (300) each arranged on the pixel electrode and comprising a first semiconductor layer (310), a second semiconductor layer (320), and an active layer (330) disposed between the first semiconductor layer and the second semiconductor layer; a first via layer (261) disposed between the pixel electrode and the light emitting elements; a first reflective layer (211) disposed on the first via layer and surrounding the side surfaces of the light emitting elements; a second via (530) layer disposed on the first via layer and the first reflective layer ; and a common electrode (220) disposed on the second via layer and the light emitting elements. See notes above for broadest reasonable interpretation of “on”, “disposed” [0075, 0089, 0110-0120]. [0107: Cho discloses multiple stacks of electrode layers 212 and 211] . Regarding Claim 1 2 , Cho discloses in Fig 2: The display device of claim 11, wherein each of the light emitting elements further comprises a connection electrode (550) disposed between the pixel electrode (211) and the first semiconductor layer (310) , and a height of the first via layer and a height of the connection electrode are same (See Fig 2). A figure teaches everything it shows to a person having ordinary skill in the art. See In re Mraz, 455 F.2d 1069, 1071 (CCPA 1972) (figures can be relied upon for what they show.)2111 . Regarding Claim 1 3 , Cho discloses in Fig 2: The display device of claim 11, wherein a top surface of the first via layer (261) and a bottom surface of the first semiconductor layer (310) contact (indirectly) each other. Regarding Claim 1 4 , Cho discloses in Fig 2: The display device of claim 11, wherein each of the light emitting elements (300) further comprises an insulating layer (380) surrounding side surfaces of the first semiconductor layer (310) , the active layer (330) , and the second semiconductor layer (320) , and the first reflective layer (211) contacts (indirectly) the insulating layer (380) . Regarding Claim 1 5 , Cho discloses in Fig 2: The display device of claim 11, wherein the first reflective layer (211) surrounds side surfaces of the first semiconductor layer (310) , the active layer (330) , and the second semiconductor layer (320) . Regarding Claim 1 6 , Cho discloses in Fig 2: The display device of claim 11, further comprising: a second reflective layer (221) disposed on the first via layer (261) , wherein the first via layer (261) comprises a protrusion overlapping the bank layer (410) in a plan view, and the second reflective layer (221) is disposed on a side surface of the protrusion (See Fig 2) . Regarding Claim 1 7 , Cho discloses in Fig 2: The display device of claim 16, wherein the first reflective layer (211) surrounds a side surface of the second semiconductor layer (320) , and a bottom surface of the first reflective layer is disposed higher than a top surface of the active layer (330) See Fig 2 . Regarding Claim 1 8 , Cho discloses in Fig 2: The display device of claim 16, wherein each of the first reflective layer (211) and the second reflective layer (221) surrounds the light emitting elements (300) and has a closed loop shape in a plan view (See Fig 1) . Regarding Claim 20 , Cho discloses in Fig 2: The display device of claim 16, wherein a bottom surface of the second reflective layer (221) is disposed higher than a top surface of the active layer (330) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US 2021/0167050 A1 hereinafter Cho) in view of Kim, Duk (WO 2021/091061 hereinafter Duk with US 2022/0406759 A1 being used as a English language equivalent) . Regarding Claim 10, Cho discloses in Fig 2: The display device of claim 1 , Cho further discloses: further comprising: the common electrode (221) and overlapping the bank layer in a plan view; a second reflective layer (221: Cho discloses presence of multiple layers of 221 and 222) disposed on the bank (410) ; a wavelength conversion layer disposed between the partition walls; and a color filter layer disposed on the wavelength conversion layer [not illustrated in Figs ; disclosed in 0051], [0094, 0107] Cho does not disclose: partition walls overlapping the bank layer in a plan view . However, Duk discloses that the bank layer (410) has multiple layers (411/412/417) that overlap one another in plan view (See Fig 6 ) . References Cho and Duk are analogous art because they both are directed to LED devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Cho with the specified features of Duk because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Cho and Duk so that partition walls overlapping the bank layer in a plan view as taught by Duk in Cho’s device since, this improve s luminous efficiency [0184]. Allowable Subject Matter The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 1 9 , the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “wherein the second reflective layer does not overlap the first semiconductor layer and the active layer in a horizontal direction ” as recited in claim 1 9 in combination with the remaining features. The most relevant prior art references, Cho et al (US 2021/0167050 A1 hereinafter Cho) in Fig 2 substantially teache s the limitations of the claim 1 9 , with the exception of the limitations described in the preceding paragraph. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT NISHATH YASMEEN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7564 . 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Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NISHATH YASMEEN/ Primary Examiner, Art Unit 2811