DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Office Action is in response to amendments and remarks filed on 11/10/2025. Claims 1-12 are currently pending.
Claim Objections
Claim 1 is objected to because of the following informalities:
3. Claim 1 recites “an array of photo-detecting devices”. Should this read as “an array of the photo-detecting devices”?
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
5. Claims 1-9, 11-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C.112, the applicant), regards as the invention.
Claim 1 recites “a second signal processor”, line 6; then line 11, recites “each second signal processor”. Is there one second signal processor or multiple second signal processors?
Claims 2-9, 11-12 are indefinite due to their dependencies.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tsukuda et al., (US 2023/0396898 A1)
Regarding claim 1, Tsukuda et al., disclose a system comprising a first signal processor (61 combined with 62a, Fig.4) implemented using only one type of a n-channel metal oxide semiconductor (NMOS) (62a) or a p-channel metal oxide semiconductor (PMOS) (see Fig.4, the processor 61 includes the transistor 62a to generate a processed output signal, and [0084], the transistor 62a according to the present embodiment is an nMOS) on a substrate (52, see Fig.3, and [0069], the state detection circuits 61 are disposed, for example, in the logic array unit 53 on the substrate 52) and configured to output a detection signal (S3, Fig.4 ) of a photo-detecting device (41 including the APD 41a, see Fig.4); and
a second signal processor (63 and the wired NOR circuit 62b, Fig. 4) disposed in a position where the second signal processor is spaced apart from the first signal processor (Figs. 3, 4 and paragraph [0069], “The state detection circuits 61 are disposed, for example, in the logic array unit 53 so as to face the pixel array region 42. On the other hand, for example, the TDC 63 is disposed in the signal processing unit 54 so as not to face the pixel array region 42), on the substrate (52, Figs. 3,4), and configured to control a dead time of the photo-detecting device (Fig.4 and paragraph [0082], The signal S4 is output from the second processor, the wired NOR circuit 62b; and [0090], “The signal S4 thus fed back is input to the R terminal of each DFF circuit 61 a. As a result, each DFF circuit 61 a is asynchronously reset”, and [0094], “when any one of the pixels 41 illustrated in FIG. 4 receives a photon, each DFF circuit 61 a is reset in a propagation delay time of the signal S4 and a reset propagation delay time of each DFF circuit 61 a. This allows, when any one of the pixels 41 illustrated in FIG. 4 receives a photon, the APD sensor according to the present embodiment to return to a state where the next photon can be detected after the end of a reset period having a predetermined length”. This is controlling the deadtime because when the reset completes, the sensor is ready to detect again), wherein the first signal processor (61) is disposed on a pixel-by-pixel basis one-to-one mapping with the photo-detecting device (41a, Fig.4), each second signal processor (63 includes 62b) is arranged outside an array of photo-detecting devices (41a)( see Figs.3, 4 and [0069], the TDC 63 is disposed in the signal processing unit 54 so as not to face the pixel array region), and is connected to a plurality of the first signal processors (61) arranged in each column or each row of the array of the photo-detecting devices (41, see Fig.4).
Regarding claim 4, Tsukuda et al., as discussed in claim 1, disclose (Fig.4) the first signal processor (61) being implemented with an NMOS (62a, (see Fig.4, the processor 61 includes the transistor 62a to generate a processed output signal, and [0084], “transistor 62 a according to the present embodiment is an nMOS”) and the second signal processor (63 and 62b) is implemented with a PMOS (62d, see Fig.4, the second processor 63 and 62b includes the transistor 62d which is the pMOS), or the first signal processor is implemented with a PMOS and the second signal processor is implemented with an NMOS.
Regarding claim 5, Tsukuda et al., as discussed in claim 1, disclose (Fig.4) the first signal processor (61 including the 62a) being disposed on a pixel-by-pixel basis one-to-one mapping with the photo-detecting device (41a), and the second signal processor (63 including 62b) is disposed on a column-by-column basis or on a row- by-row basis in an array of photo-detecting devices (see Fig.4, the second processor 63 and 62b is a shared resource organized by rows or columns).
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Tsukuda et al., in view of Henderson et al., (US 2010/0019295 A1).
Regarding claim 2, Tsukuda et al., as discussed in claim 1, disclose the first signal processor (61, Fig.4) being implemented with an NMOS (62a, Each transistor 62 a according to the present embodiment is an nMOS, [0079]). Tsukuda et al., do not disclose the single-photon avalanche diode (SPAD) implemented in an N-well as claimed. Henderson et al., disclose the photo-detecting device comprising a single-photon avalanche diode (SPAD) implemented in an N-well , and the first signal processor is implemented with an NMOS (paragraph [0061], “a SPAD and NMOS transistor sharing the same deep n-well”, and “These NMOS devices may be connected in such a way as to perform quenching and readout operations on a SPAD”, which indicates the NMOS devices being as the signal processor). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tsukuda et al., by utilizing the teaching of Henderson et al., to improve and reduce substrate noise.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Tsukuda et al., in view of Shimada et al., (US 2024/0213281 A1).
Regarding claim 3, Tsukuda et al., as discussed in claim 1, discloses the first signal processor (61) being implemented with a PMOS (“Each transistor 62 a may be a pMOS”, [0079]). Tsukuda et al., does not disclose the charge focusing SPAD that requires applying of a negative (-) voltage to the substrate as claimed. Shimada et al., disclose charge focusing SPAD that requires applying of a negative (-) voltage to a substrate (paragraph [0136], “a negative voltage larger than that of the anode electrode (contact electrode 52) of the SPAD 21 is applied from the front surface side of the semiconductor substrate 31 “). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tsukuda et al., by utilizing the teaching of Shimada et al., so that the system can easy to collect carriers in a high electric field region, and improve the spad’s performance (Shimada et al, [0138]).
Claims 6, 7 are rejected under 35 U.S.C. 103 as being unpatentable over Tsukuda et al., in view of Webster et al., (US 2013/0193546 A1).
Regarding claims 6 and 7, Tsukuda et al., as discussed in claim 5, does not disclose a plurality of first signal processors being implemented in a common N-well or P-well on a row-by-row basis or on a column-by-column basis, and the second signal processor is implemented in a common N-well or P-well outside the array of photo-detecting devices as claimed. Webster et al., disclose a plurality of first signal processors are implemented in a common N-well or P-well on a row-by-row basis or on a column-by-column basis (see Fig.16), and the second signal processor is implemented in a common N-well or P-well outside the array of photo-detecting devices (outside the active spad region) (see Fig. 16). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tsukuda et al., by utilizing the teaching of Webster et al., to improve and reduce substrate noise.
Allowable Subject Matter
8. Claim 10 is allowable.
9. Claims 8-9, 11-12 would be allowed once the 112b rejection is overcome.
10. Claims 8-9, 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 8 and 10: The prior art fails to disclose a signal detector configured to detect and output a voltage of an output terminal of the photo-detecting device: and a recharge unit configured to drop the voltage of the output terminal of the photo- detecting device in response to a control signal received from the second signal processor after the detection signal is output and to convert the photo-detecting device into an operable state, wherein the signal detector is disposed on a pixel-by- pixel basis one-to-one mapping with the photo-detecting device, and the recharge unit is commonly disposed on a column-by-column basis or on a row-by-row basis in the array of photo-detecting devices.
Claims 9, 11, 12 depend on claim 8.
Response to Arguments
11. Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
12. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/M.T.T./Examiner, Art Unit 2878
/TONY KO/Primary Examiner, Art Unit 2878