DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-17 and 20 are objected to because of the following informalities:
Claim 1 recites “the second package substate,.” (line 11) which should be replaced with
“the second package substate.”
Claim 20 recites “the semiconductor chip” (line 8) which should be replaced with
“the at least one semiconductor chip” for consistency with claim language.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2014/0133105 to Yee et al. (hereinafter Yee).
With respect to claim 1, Yee discloses a semiconductor package (e.g., package-on-package (POP) packaging system with high power chip and low power chip, see the annotated Fig. 3 below) (Yee, Fig. 3, ¶0002, ¶0007-¶0008, ¶0026-¶0035) comprising:
a first package substrate (304) (Yee, Fig. 3, ¶0026, ¶0031-¶0032) comprising a first redistribution layer;
at least one semiconductor chip (101) (Yee, Fig. 3, ¶0015, ¶0026-¶0027) on the first redistribution layer (304) and comprising a semiconductor device (e.g., logic device) (Yee, Fig. 3, ¶0015, ¶0026-¶0027); and
a second package substrate (302) (Yee, Fig. 3, ¶0026, ¶0029, ¶0032) on the at least one semiconductor chip (101) and comprising a second redistribution layer,
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wherein the at least one semiconductor chip (101) comprises at least one heat dissipation via (e.g., through-silicon vias 344 connected to the conductive wires 312a through the bond pads 330 to spread heat from high-power chip 101) (Yee, Fig. 3, ¶0029-¶0030) configured as a dissipation path of heat generated from the semiconductor device (101), and
the at least one heat dissipation via (344) (Yee, Fig. 3, ¶0029-¶0030) having one end (e.g., a lower end) adjacent to the semiconductor device (101) and penetrating through at least a portion of the at least one semiconductor chip, and another end (e.g., an upper end) contacting the second package substrate (302).
Regarding claim 2, Yee discloses the semiconductor package of claim 1. Further, Yee discloses the semiconductor package, further comprising: a molding layer (305) (Yee, Fig. 3, ¶0028-¶0029) between the first package substrate (304) and the second package substrate (302) to surround the at least one semiconductor chip (101), wherein the another end (e.g., the upper end) of the heat dissipation via (344) (Yee, Fig. 3, ¶0029-¶0030) contacts (e.g., through the bond pads 330) the molding layer (305).
Regarding claim 3, Yee discloses the semiconductor package of claim 1. Further, Yee discloses the semiconductor package, wherein the another end (e.g., the upper end) of the at least one heat dissipation via (344) is connected to the second redistribution layer (302) (Yee, Fig. 3, ¶0029-¶0030).
Regarding claim 4, Yee discloses the semiconductor package of claim 3. Further, Yee discloses the semiconductor package, further comprising: a first connection terminal (e.g., bond pads 368) (Yee, Fig. 3, ¶0029-¶0030) between the at least one semiconductor chip (101) and the first redistribution layer (304) and connecting the at least one semiconductor chip (101) and the first redistribution layer (304) to each other; and at least one connection structure (316A/316B) (Yee, Fig. 3, ¶0032-¶0033) connecting the first redistribution layer (304) and the second redistribution layer (302) to each other.
Regarding claim 5, Yee discloses the semiconductor package of claim 4. Further, Yee discloses the semiconductor package, wherein the second redistribution layer (302) comprises: redistribution lines (e.g., 312C/312B) (Yee, Fig. 3, ¶0032) connected to the at least one connection structure (e.g., 316B); and a heat dissipation pattern (312A/346/330, the through-silicon vias 344 connected to the conductive wires 312a through the bond pads 330 and conductive vias 346 to spread heat from high-power chip 101) (Yee, Fig. 3, ¶0029-¶0030) insulated from the redistribution lines (312C/312B), and the at least one heat dissipation via (344) is connected to the heat dissipation pattern (312A/346/330).
Regarding claim 6, Yee discloses the semiconductor package of claim 5. Further, Yee discloses the semiconductor package, wherein the at least one heat dissipation via (e.g., through-silicon vias 344 connected to the conductive wires 312a through the bond pads 330 to spread heat from high-power chip 101) (Yee, Fig. 3, ¶0029-¶0030) has an upper surface directly contacting a lower surface (e.g., a lower surface of the bond pad 330) of the heat dissipation pattern (312A/346/330).
Regarding claim 7, Yee discloses the semiconductor package of claim 6. Further, Yee discloses the semiconductor package, wherein at least a portion of the redistribution lines (e.g., an upper surface of the wires 312B connected to the connection structure 316B) (Yee, Fig. 3, ¶0029-¶0032) are coplanar with the heat dissipation pattern (e.g., an upper surface of the wire 312A of the heat dissipation pattern 312A/346/330).
With respect to claim 18, Yee discloses a package-on-package type semiconductor package (e.g., package-on-package (POP) packaging system with high power chip and low power chip, see the annotated Fig. 3 above) (Yee, Fig. 3, ¶0002, ¶0007-¶0008, ¶0026-¶0035) comprising a first semiconductor package (310) and a second semiconductor package (102), wherein at least one (e.g., 310) of the first semiconductor package (310) and the second semiconductor package (102) comprises:
a first package substrate (304) (Yee, Fig. 3, ¶0026, ¶0031-¶0032) comprising a first redistribution layer;
at least one semiconductor chip (101) (Yee, Fig. 3, ¶0015, ¶0026-¶0027) on the first redistribution layer (304);
a first connection terminal (368) (Yee, Fig. 3, ¶0030-¶0031) between the at least one semiconductor chip (101) and the first redistribution layer (304) and connecting the at least one semiconductor chip (101) and the first redistribution layer (304);
a second package substrate (302) (Yee, Fig. 3, ¶0026, ¶0029, ¶0032) on the at least one semiconductor chip (101) and comprising a second redistribution layer; and
at least one connection structure (316A/316B) (Yee, Fig. 3, ¶0032-¶0033) connecting the first redistribution layer (304) and the second redistribution layer (302) to each other, and the at least one semiconductor chip (101) comprises at least one heat dissipation via (e.g., through-silicon vias 344 connected to the conductive wires 312a through the bond pads 330 to spread heat from high-power chip 101) (Yee, Fig. 3, ¶0029-¶0030) penetrating through at least a portion of the at least one semiconductor chip (101) and connected to the second redistribution layer (302).
Regarding claim 19, Yee discloses the package-on-package type semiconductor package of claim 18. Further, Yee discloses the semiconductor package, wherein the at least one heat dissipation via (344) (Yee, Fig. 3, ¶0029-¶0030) has one end (e.g., an upper end) connected to the second redistribution layer (302) and another end (e.g., a lower end) adjacent to a semiconductor device (e.g., logic device) (Yee, Fig. 3, ¶0015, ¶0026-¶0027) within the at least one semiconductor chip (101).
With respect to claim 20, Yee discloses an electronic system (300) comprising a main board (e.g., PCB 190) and a semiconductor package (e.g., package-on-package (POP) packaging system with high power chip and low power chip, see the annotated Fig. 3 above) (Yee, Fig. 3, ¶0002, ¶0007-¶0008, ¶0026-¶0035) mounted on the main board (190), wherein the semiconductor package comprising:
a first package substrate (304) (Yee, Fig. 3, ¶0026, ¶0031-¶0032) comprising a first redistribution layer;
at least one semiconductor chip (101) (Yee, Fig. 3, ¶0015, ¶0026-¶0027) on the first redistribution layer (304) and comprising a semiconductor device (e.g., logic device) (Yee, Fig. 3, ¶0015, ¶0026-¶0027); and
a second package substrate (302) (Yee, Fig. 3, ¶0026, ¶0029, ¶0032) on the at least one semiconductor chip (101) and comprising a second redistribution layer,
the semiconductor chip (101) comprises at least one heat dissipation via (e.g., through-silicon vias 344 connected to the conductive wires 312a through the bond pads 330 to spread heat from high-power chip 101) (Yee, Fig. 3, ¶0029-¶0030) configured as a heat dissipation path of heat generated from the semiconductor device (101),
the at least one heat dissipation via (344) (Yee, Fig. 3, ¶0029-¶0030) having one end (e.g., a lower end) adjacent to the semiconductor device (101) and penetrating through at least a portion of the at least one semiconductor chip, and another end (e.g., an upper end) contacting the second package substrate (302).
Claims 1, 3-4, and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2014/0225248 to Henderson et al. (hereinafter Henderson).
With respect to claim 1, Henderson discloses a semiconductor package (e.g., stacked integrated circuits, see the annotated Fig. 4 below) (Henderson, Figs. 3-4, ¶0032, ¶0009-¶0015, ¶0049-¶0056) comprising:
a first package substrate (402) (Henderson, Fig. 4, ¶0049, ¶0056, ¶0084) comprising a first redistribution layer (e.g., power distribution network including interconnects 434-436);
at least one semiconductor chip (404/406) (Henderson, Fig. 4, ¶0049, ¶0056, ¶0084) on the first redistribution layer (402) and comprising a semiconductor device (e.g., 418/422) (Henderson, Fig. 4, ¶0049-¶0051, ¶0056, ¶0084-¶0085); and
a second package substrate (e.g., 409) (Henderson, Fig. 4, ¶0056, ¶0089) on the at least one semiconductor chip (404/406) and comprising a second redistribution layer (e.g., interconnect layers 411/412 in the insulator layer 410),
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wherein the at least one semiconductor chip (e.g., 406) comprises at least one heat dissipation via (e.g., vias 426/428 connected to the heat spreader 409 including interconnects 411/412) (Henderson, Fig. 4, ¶0051, ¶0056) configured as a dissipation path of heat generated from the semiconductor device (404/406), and
the at least one heat dissipation via (426/428) (Henderson, Fig. 4, ¶0051, ¶0056) having one end (e.g., a lower end 428) adjacent to the semiconductor device (422) and penetrating through at least a portion of the at least one semiconductor chip, and another end (e.g., an upper end 426) contacting the second package substrate (409).
Regarding claim 3, Henderson discloses the semiconductor package of claim 1. Further, Henderson discloses the semiconductor package, wherein the another end (e.g., the upper end 428) of the at least one heat dissipation via (426/428) is connected to the second redistribution layer (411) (Henderson, Fig. 4, ¶0056).
Regarding claim 4, Henderson discloses the semiconductor package of claim 3. Further, Henderson discloses the semiconductor package, further comprising: a first connection terminal (e.g., solder balls or bumps) (Henderson, Fig. 4, ¶0062) between the at least one semiconductor chip (e.g., 404) and the first redistribution layer (e.g., interconnect of the package substrate 402) and connecting the at least one semiconductor chip (404) and the first redistribution layer (402) to each other; and at least one connection structure (e.g., through-mold vias TMVs 414/416) (Henderson, Fig. 4, ¶0055-¶0056) connecting the first redistribution layer (402) and the second redistribution layer (411) to each other.
With respect to claim 18, Henderson discloses a package-on-package type semiconductor package (e.g., stacked integrated circuits on package substrate, see the annotated Fig. 4 above) (Henderson, Figs. 3-4, ¶0032, ¶0009-¶0015, ¶0049-¶0056) comprising a first semiconductor package (418/420) and a second semiconductor package (422/424), wherein at least one (e.g., 422/424) of the first semiconductor package and the second semiconductor package comprises:
a first package substrate (Henderson, Fig. 4, ¶0049, ¶0056, ¶0084) comprising a first redistribution layer (e.g., power distribution network including interconnects 434-436);
at least one semiconductor chip (406) (Henderson, Fig. 4, ¶0049, ¶0056, ¶0084) on the first redistribution layer (402);
a first connection terminal (solder balls/bumps) (Henderson, Fig. 4, ¶0062) between the at least one semiconductor chip (406) and the first redistribution layer (402) and connecting the at least one semiconductor chip (406) and the first redistribution layer (402);
a second package substrate (409) (Henderson, Fig. 4, ¶0056, ¶0089) on the at least one semiconductor chip (406) and comprising a second redistribution layer (e.g., interconnect layers 411/412 in the insulator layer 410); and
at least one connection structure (e.g., through-mold vias TMVs 414/416) (Henderson, Fig. 4, ¶0055-¶0056) connecting the first redistribution layer (e.g., interconnect of the package substrate 402) and the second redistribution layer (e.g., interconnect 411/412 of the package substrate 409) to each other, and the at least one semiconductor chip (406) comprises at least one heat dissipation via (e.g., vias 426/428 connected to the heat spreader 409) (Henderson, Fig. 4, ¶0051, ¶0056) penetrating through at least a portion of the at least one semiconductor chip (406) and connected to the second redistribution layer (411).
Regarding claim 19, Henderson discloses the package-on-package type semiconductor package of claim 18. Further, Henderson discloses the semiconductor package, wherein the at least one heat dissipation via (426/428) (Henderson, Fig. 4, ¶0051, ¶0056) has one end (e.g., an upper end 426) connected to the second redistribution layer (411) and another end (e.g., a lower end 428) adjacent to a semiconductor device (e.g., 422) (Henderson, Fig. 4, ¶0050, ¶0056) within the at least one semiconductor chip (406).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Regarding claim 8, Yee discloses the semiconductor package of claim 7. Further, Yee does not specifically disclose that
Claims 8-10 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0133105 to Yee in view of Lin (US 2014/0339707).
Regarding claim 8, Yee discloses the semiconductor package of claim 7. Further, Yee does not specifically disclose that the at least one semiconductor chip further comprises a semiconductor substrate on which the semiconductor device is mounted, and the at least one heat dissipation via penetrates through at least a portion of the semiconductor substate when viewed in plan view.
However, Lin teaches forming a semiconductor package (Lin, Figs. 1-6, ¶0013-¶0037), wherein the at least one semiconductor chip (e.g., stacked dies 10) (Lin, Figs. 1-2, 6, ¶0013-¶0014) further comprises a semiconductor substrate (20) on which the semiconductor device (22) is mounted, and the at least one heat dissipation via (26A/26B) penetrates through at least a portion of the semiconductor substate (20) when viewed in plan view (Lin, Figs. 4-5, ¶0028-¶0029), to provide a seal-ring-comprising thermal path to effectively remove heat generated in the stacked semiconductor dies (10).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Yee by forming a stacked die structure including at least one semiconductor chip having an active device on a semiconductor substrate and surrounded by the thermal through-substrate vias as taught by Lin to have the semiconductor package, wherein the at least one semiconductor chip further comprises a semiconductor substrate on which the semiconductor device is mounted, and the at least one heat dissipation via penetrates through at least a portion of the semiconductor substate when viewed in plan view, in order to provide improved three-dimensional integrated circuit comprising a seal-ring-comprising thermal path to effectively remove heat generated in the stacked semiconductor dies (Lin, ¶0003, ¶0013-¶0014, ¶0021, ¶0024, ¶0028-¶0029).
Regarding claim 9, Yee in view of Lin discloses the semiconductor package of claim 8. Further, Yee does not specifically disclose that the at least one heat dissipation via is in a location adjacent to the semiconductor device, or disposed to overlap the semiconductor device when viewed in plan view.
However, Lin teaches forming the semiconductor package (Lin, Figs. 1-6, ¶0013-¶0037), wherein the at least one heat dissipation via (e.g., 26A) is in a location adjacent to the semiconductor device (22) when viewed in plan view (Lin, Figs. 4-5, ¶0028-¶0029), to provide a seal-ring-comprising thermal path to effectively remove heat generated in the stacked semiconductor dies (10).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Yee/Lin by forming at least one semiconductor chip having an active device on a semiconductor substrate and surrounded by the thermal through-substrate vias as taught by Lin to have the semiconductor package, wherein the at least one heat dissipation via is in a location adjacent to the semiconductor device when viewed in plan view, in order to provide improved three-dimensional integrated circuit comprising a seal-ring-comprising thermal path to effectively remove heat generated in the stacked semiconductor dies (Lin, ¶0003, ¶0013-¶0014, ¶0021, ¶0024, ¶0028-¶0029).
Regarding claim 10, Yee in view of Lin discloses the semiconductor package of claim 9. Further, Yee does not specifically disclose that an area of the at least one heat dissipation via is 20% or more of an area of the semiconductor device when viewed in plan view.
However, Lin teaches forming the at least one heat dissipation via (26A) (Lin, Figs. 4-5, ¶0021, ¶0023, ¶0028) having a specific diameter in the plan view to form a seal-ring structure (60), and that increasing a width and a pitch of the seal-ring structure (60) would increase the heat dissipation efficiency (Lin, Figs. 4-5, ¶0028). The seal structure including the at least one heat dissipation via (26A) has uniform pitch between 0.4 mm to 50 mm.
Further, a person of ordinary skill in the art would recognize that with an area of the semiconductor device of about 16 mm2, an area of the at least one heat dissipation via of about 3.2 mm2 would be 20% of an area of the semiconductor device, and that with an increase of the area of the at least one heat dissipation via, the seal structure including a plurality of heat dissipation vias would form a continuous seal-ring-comprising thermal path to increase the heat dissipation efficiency (Lin, Figs. 4-5, ¶0028).
Thus, Lin recognizes that the doping concentration a width and a pitch of the seal-ring structure impacts heat dissipation efficiency of the semiconductor package. Thus, a width and a pitch of the seal-ring structure are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a width and a pitch of the seal-ring structure as Lin has identified a width and a pitch of the seal-ring structure as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at a specific area of the at least one heat dissipation via of the seal-ring structure to have an area of the at least one heat dissipation via is 20% or more of an area of the semiconductor device when viewed in plan view, in order to form a continuous seal-ring-comprising thermal path to increase the heat dissipation efficiency as taught by Lin (¶0028) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Yee/Lin by optimizing an area of the at least one heat dissipation via of the seal ring structure as taught by Lin to have the semiconductor package, wherein an area of the at least one heat dissipation via is 20% or more of an area of the semiconductor device when viewed in plan view, in order to form a continuous seal-ring-comprising thermal path to increase the heat dissipation efficiency (Lin, ¶0003, ¶0013-¶0014, ¶0021, ¶0024, ¶0028-¶0029).
Regarding claim 13, Yee discloses the semiconductor package of claim 4. Further, Yee discloses the semiconductor package, wherein the at least one semiconductor chip comprises: a first semiconductor chip (101) disposed on the first redistribution layer (304), but does not specifically disclose a second semiconductor chip disposed on the first semiconductor chip.
However, Lin teaches forming a semiconductor package (Lin, Figs. 1-6, ¶0013-¶0037), wherein the at least one semiconductor chip includes stacked dies (10) (Lin, Figs. 1-2, 6, ¶0013-¶0014) such that a first semiconductor chip (e.g., bottom die 10) is disposed on the first redistribution layer (e.g., RDLs 30); and a second semiconductor chip (e.g., an upper die 10) (Lin, Figs. 1-2, 6, ¶0022-¶0028) disposed on the first semiconductor chip, to provide improved three-dimensional integrated circuit comprising a seal-ring-comprising thermal path to effectively remove heat generated in the stacked semiconductor dies (Lin, ¶0003, ¶0013-¶0014, ¶0021, ¶0024, ¶0028-¶0029).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Yee by forming a stacked die structure including a plurality of semiconductor chips as taught by Lin to have the semiconductor package, wherein a second semiconductor chip disposed on the first semiconductor chip, in order to provide improved three-dimensional integrated circuit comprising a seal-ring-comprising thermal path to effectively remove heat generated in the stacked semiconductor dies (Lin, ¶0003, ¶0013-¶0014, ¶0021, ¶0024, ¶0028-¶0029).
Regarding claim 14, Yee in view of Lin discloses the semiconductor package of claim 13. Further, Yee discloses the semiconductor package, wherein the first semiconductor chip (101) comprises a through-via (344) penetrating through at least a portion of the first semiconductor chip (101), and a first heat dissipation via (e.g., one of the silicon-through vias 344 connected to the conductive wires 312a through the bond pads 330 to spread heat from high-power chip 101) (Yee, Fig. 3, ¶0029-¶0030) from among the at least one heat dissipation via (344) penetrating through at least a portion of the first semiconductor chip (101), but does not specifically disclose that the second semiconductor chip comprises a second heat dissipation via from among the at least one heat dissipation via penetrating through the second semiconductor chip and having one end connected to the first heat dissipation via and another end connected to the second redistribution layer.
However, Lin teaches forming the stacked dies (10) (Lin, Figs. 1-2, 6, ¶0013-¶0014) including the second semiconductor chip (e.g., an upper die 10) that comprises a second heat dissipation via (e.g., the via 26A of the upper die 10) (Lin, Figs. 1-2, 6, ¶0022-¶0028) from among the at least one heat dissipation via penetrating through the second semiconductor chip (10) and having one end connected to the first heat dissipation via (e.g., the via 26A of the lower die 10) and another end connected to the second redistribution layer (e.g., the RDLs 30 formed on the upper die 10), to provide improved three-dimensional integrated circuit comprising a seal-ring-comprising thermal path to effectively remove heat generated in the stacked semiconductor dies (Lin, ¶0003, ¶0013-¶0014, ¶0021, ¶0024, ¶0028-¶0029).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Yee/Lin by forming a stacked die structure including a plurality of semiconductor chips as taught by Lin to have the semiconductor package, wherein the second semiconductor chip comprises a second heat dissipation via from among the at least one heat dissipation via penetrating through the second semiconductor chip and having one end connected to the first heat dissipation via and another end connected to the second redistribution layer, in order to provide improved three-dimensional integrated circuit comprising a seal-ring-comprising thermal path to effectively remove heat generated in the stacked semiconductor dies (Lin, ¶0003, ¶0013-¶0014, ¶0021, ¶0024, ¶0028-¶0029).
Regarding claim 15, Yee in view of Lin discloses the semiconductor package of claim 14. Further, Yee does not specifically disclose the semiconductor package, wherein the first semiconductor chip comprises a first semiconductor substrate and a first semiconductor device provided on the first semiconductor substrate, and the second semiconductor chip comprises a second semiconductor substrate and a second semiconductor device provided on the second semiconductor substrate, and the through-via and the first heat dissipation via penetrate through the first semiconductor substrate, and the second heat dissipation via penetrates through the second semiconductor substrate.
However, Lin teaches forming a semiconductor package (Lin, Figs. 1-6, ¶0013-¶0037), wherein the first semiconductor chip (e.g., the lower die 10) (Lin, Figs. 1-2, 6, ¶0013-¶0014, ¶0022-¶0023) comprises a first semiconductor substrate (20) and a first semiconductor device (22) provided on the first semiconductor substrate, and the second semiconductor chip (e.g., the upper die 10) comprises a second semiconductor substrate (20) and a second semiconductor device (22) provided on the second semiconductor substrate, and the through-via (26B) and the first heat dissipation via (26A) penetrate through the first semiconductor substrate (e.g., the lower substrate 20), and the second heat dissipation via (26A) penetrates through the second semiconductor substrate (e.g., the upper substrate 20), to form a seal-ring-comprising thermal path (60) (Lin, Fig. 2, ¶0024).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Yee/Lin by forming a stacked die structure including a semiconductor substrate and a semiconductor device surrounded by the thermal through-substrate vias as taught by Lin to have the semiconductor package, wherein the first semiconductor chip comprises a first semiconductor substrate and a first semiconductor device provided on the first semiconductor substrate, and the second semiconductor chip comprises a second semiconductor substrate and a second semiconductor device provided on the second semiconductor substrate, and the through-via and the first heat dissipation via penetrate through the first semiconductor substrate, and the second heat dissipation via penetrates through the second semiconductor substrate, in order to provide improved three-dimensional integrated circuit comprising a seal-ring-comprising thermal path to effectively remove heat generated in the stacked semiconductor dies (Lin, ¶0003, ¶0013-¶0014, ¶0021, ¶0024, ¶0028-¶0029).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0133105 to Yee in view of Henderson (US 2014/0225248).
Regarding claims 11-12, Yee discloses the semiconductor package of claim 6. Further, Yee does not specifically disclose that an upper diameter of the at least one heat dissipation via is greater than a lower diameter of the at least one heat dissipation via when viewed in plan view (as claimed in claim 11); wherein the at least one heat dissipation via comprises: a lower via having a first diameter; and an upper via having a second diameter, greater than the first diameter (as claimed in claim 12).
However, Henderson taches forming a package (Henderson, Figs. 3-4, ¶0009-¶0015, ¶0043, ¶0049-¶0056) comprising stacked semiconductor dies (e.g., 304/306 or 404/406), wherein the second die (306 or 406) includes a via structure (e.g., 326/328 or 426/428) (Henderson, Figs. 3-4, ¶0051, ¶0056) comprising a first upper via (e.g., 326 or 426) coupled to the heat spreader (e.g., 310/312 or 409) and having a first width/diameter, and a second lower via (e.g., 328 or 428) coupled to the first upper via and having a second width/diameter smaller than the first width/diameter. In Henderson, different widths/diameters of the vias provide strength, mechanical stability/rigidity of the coupling between the heat spreader and the second die, and the use of larger vias improves the thermal conductivity of the second die because the larger vias improve and/or increase the amount of heat that is dissipated from the second die.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Yee by forming a stacked die structure including a second die coupled to a heat spreader by using the through-substrate vias having different diameters as taught by Henderson to have the semiconductor package, wherein an upper diameter of the at least one heat dissipation via is greater than a lower diameter of the at least one heat dissipation via when viewed in plan view (as claimed in claim 11); wherein the at least one heat dissipation via comprises: a lower via having a first diameter; and an upper via having a second diameter, greater than the first diameter (as claimed in claim 12), in order to provide strength, mechanical stability/rigidity of the coupling between the heat spreader and the second die, and to improve the thermal conductivity of the second die by increasing the amount of heat that is dissipated from the second die (Henderson, ¶0009-¶0015, ¶0051, ¶0056)
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0133105 to Yee in view of Lin (US 2014/0339707) as applied to claim 14, and further in view of Katkar et al. (US 2015/0255429, hereinafter Katkar).
Regarding claim 16, Yee in view of Lin discloses the semiconductor package of claim 14. Further, Yee does not specifically disclose the semiconductor package, wherein a cross-sectional view of at least one of the first heat dissipation via or the second heat dissipation via is larger than a cross- sectional area of the through-via.
However, Katkar teaches forming a semiconductor package comprising three-dimensional (3D) packaged component (Katkar, Fig. 3, ¶0001, ¶0005-¶0006, ¶0027-¶0034, ¶0046-¶0048) including multiple stacked dies (10-1/10-2/10-3) having thermal via structures (118) (Katkar, Fig. 3, ¶0047) for conducting heat in a vertical direction in the 3D packaged component, and signal vias (18) (Katkar, Fig. 3, ¶0048, ¶0027-¶0034) for conducting a signal, supply power, or supply voltage, wherein a cross-sectional view of at least one of the first heat dissipation via (e.g., thermal via 118 of the lower die 10-3) or the second heat dissipation via (e.g., thermal via 118 of the upper die 10-2/10-1) is larger than a cross- sectional area of the through-via (18), to increase heat conduction in a vertical direction in the 3D packaged component.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Yee/Lin by forming a semiconductor package comprising 3D packaged component including multiple stacked dies as taught by Katkar to have the semiconductor package, wherein a cross-sectional view of at least one of the first heat dissipation via or the second heat dissipation via is larger than a cross- sectional area of the through-via, in order to provide improved 3D integrated circuit package with increased heat conduction in a vertical direction in the 3D packaged component (Katkar, ¶0001, ¶0005-¶0006, ¶0028-¶0029, ¶0047-¶0048).
Regarding claim 17, Yee in view of Lin and Katkar discloses the semiconductor package of claim 16. Further, Yee does not specifically disclose the semiconductor package, wherein a height of the at least one of the first heat dissipation via or the second heat dissipation via is at least 8 times greater than a diameter of the at least one of the first heat dissipation via and the second heat dissipation via.
However, Katkar teaches forming a thermal via (Katkar, Fig. 3, ¶0054-¶0055) having a depth in a range from 1 mm to 200 mm, and a width in a range between 0.5 mm and 100 mm, wherein for a thin die of about 10 mm, a width is in a range between 0.5 mm and 1 mm.
Thus, a person of ordinary skill in the art would recognize that for a thin die of about 10 mm and a width of the thermal via of about 1 mm, a height of the thermal via extending through the thin substrate would be 10 times greater than a diameter of the thermal via, to efficiently conduct heat in a vertical direction in the 3D packaged component.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Yee/Lin/Katkar by forming thermal vias extending through dies of the multiple stacked dies of the 3D packaged component as taught by Katkar to have the semiconductor package, wherein a height of the at least one of the first heat dissipation via or the second heat dissipation via is at least 8 times greater than a diameter of the at least one of the first heat dissipation via and the second heat dissipation via, in order to efficiently conduct heat in a vertical direction in the 3D packaged component (Katkar, ¶0001, ¶0005-¶0006, ¶0028-¶0029, ¶0047-¶0048, ¶0054-¶0055).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891