Prosecution Insights
Last updated: July 17, 2026
Application No. 18/507,801

SUBSTRATE ALPHA PARTICLE SHIELD FOR SEMICONDUCTOR PACKAGES

Non-Final OA §102§103
Filed
Nov 13, 2023
Priority
Nov 14, 2022 — provisional 63/383,612
Examiner
BRADFORD, PETER
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology Inc.
OA Round
2 (Non-Final)
80%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
603 granted / 750 resolved
+12.4% vs TC avg
Minimal +4% lift
Without
With
+4.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
35 currently pending
Career history
790
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
80.0%
+40.0% vs TC avg
§102
6.9%
-33.1% vs TC avg
§112
12.3%
-27.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 750 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments See the new rejections below of claim 1 et seq. The applicant argues on page 10 of the response that “Independent claim 11 recites similar features to amended independent claim 1. For at least the reasons presented above with regards to independent claim 1, independent claim 11, and the claims that depend thereon, are patentable over the cited sections of the applied references.” The applicant has not amended claim 11, and also has not argued how the rejection was inadequate or improper. The applicant has not identified what “similar features” to claim 1 are specifically relied on. The applicant’s arguments on pages 8 and 9 are not directly related to claim language in 11. The applicant has not given the examiner a basis on which to reconsider the rejection of claim 11. The rejection of claim 11 and its dependent claims are maintained. See the new rejections below. Claim Interpretation Claim 1 recites “above, in a direction,” which the examiner understands to mean that the claimed direction is generally an upwardly direction. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 3, and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshinuma, JP 2004-140089 A. Claim 1: Yoshinuma discloses a substrate (11); a plurality of electrical contacts (under solder bumps 21) disposed on an outer surface of the substrate; a solder resist (12) disposed on the outer surface of the substrate and including an opening defined by a plurality of edges and exposing the plurality of electrical contacts; an alpha particle shield (30) disposed proximate to at least one edge, of the plurality of edges; and a semiconductor die (20) disposed above, in a direction, the substrate and electrically coupled to the substrate via the plurality of electrical contacts, wherein at least a portion of the alpha particle shield is disposed, in the direction, between the at least one edge and the semiconductor die (FIG. 1). PNG media_image1.png 362 716 media_image1.png Greyscale Yoshinuma discloses at [0014] that the underfill 30 can be polyimide, which is a known alpha shielding material. Claim 3: Yoshinuma discloses a polyimide layer disposed on the outer surface of the substrate and surrounding the plurality of electrical contacts, wherein the alpha particle shield is coupled to the polyimide layer. A lower part of 30 can be considered the claimed polyimide layer, and an upper portion can be considered the alpha shielding material. Claim 4: at least a portion of the polyimide layer is disposed between the solder resist and the alpha particle shield. Claims 1, 3-11, and 13-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin, US 2014/0001645 A1. Claim 1: Lin discloses a substrate (201); a plurality of electrical contacts (1101) disposed on an outer surface of the substrate (FIG. 13B); a solder resist (1301) disposed on the outer surface of the substrate and including an opening defined by a plurality of edges and exposing the plurality of electrical contacts; an alpha particle shield (1305) disposed proximate to at least one edge, of the plurality of edges; “The second UBM layers 1305 may comprise a layer of conductive material, such as a layer of titanium, or a layer of nickel…. chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, that are suitable for the formation of the second UBM layers 1305.” [0063]. Copper and nickel are known alpha shielding materials. and a semiconductor die (903) disposed above, in a direction, the substrate and electrically coupled to the substrate via the plurality of electrical contacts (FIG. 12), wherein at least a portion of the alpha particle shield is disposed, in the direction, between the at least one edge and the semiconductor die. PNG media_image2.png 284 714 media_image2.png Greyscale Claim 3: Lin discloses a polyimide layer (1303, [0062]) disposed on the outer surface of the substrate and surrounding the plurality of electrical contacts, wherein the alpha particle shield is coupled to the polyimide layer (FIG. 13B). Claim 4: at least a portion of the polyimide layer is disposed between the solder resist and the alpha particle shield (FIG. 13B). Claim 5: the alpha particle shield includes a first substantially planar portion and a second substantially planar portion extending at an angle with respect to the first substantially planar portion. PNG media_image3.png 355 762 media_image3.png Greyscale Claim 6: the first substantially planar portion extends substantially parallel to the outer surface of the substrate, and wherein the second substantially planar portion extends, from an edge of the first substantially planar portion, toward the opening of the solder resist. Claim 7: the alpha particle shield is a copper shield ([0063]). Claim 8: at least a portion of the alpha particle shield is disposed, in the direction, above the solder resist (FIG. 13B), and wherein a thickness of the alpha particle shield, in the direction, is between 2 micrometers and 10 micrometers. “The second UBM layers 1305 may be formed to have a thickness of between about 0.7 µm and about 10 µm, such as about 5 µm.” [0063]. Claim 9: the thickness of the alpha particle shield is approximately 5 micrometers ([0063]). Claim 10: the thickness of the alpha particle shield is approximately 8 micrometers ([0063]). Claim 11: Lin discloses a substrate (201); a plurality of electrical contacts (1101) disposed on an outer surface of the substrate; a solder resist (1301) disposed on the outer surface of the substrate and at least partially surrounding the plurality of electrical contacts; a semiconductor die (903, FIG. 12) electrically coupled to the substrate via the plurality of electrical contacts; and an alpha particle shield (1305) disposed between at least a portion of the solder resist and at least a portion of the semiconductor die. PNG media_image4.png 284 714 media_image4.png Greyscale Claim 13: Lin discloses a polyimide layer (1303) disposed on the outer surface of the substrate and surrounding the plurality of electrical contacts, wherein the alpha particle shield is coupled to the polyimide layer (FIG. 13B). Claim 14: at least a portion of the polyimide layer is disposed between the solder resist and the alpha particle shield (FIG. 13B). Claim 15: the alpha particle shield includes a first substantially planar portion and a second substantially planar portion extending at an angle with respect to the first substantially planar portion. PNG media_image3.png 355 762 media_image3.png Greyscale Claim 16: the first substantially planar portion extends substantially parallel to the outer surface of the substrate, and wherein the second substantially planar portion extends, from an edge of the first substantially planar portion, toward the plurality of electrical contacts. Claim 17: the alpha particle shield is a copper shield ([0063]). Claim 18: at least a portion of the alpha particle shield is disposed, in a direction, above the solder resist, and wherein a thickness of the alpha particle shield, in the direction, is between 2 micrometers and 10 micrometers. “The second UBM layers 1305 may be formed to have a thickness of between about 0.7 µm and about 10 µm, such as about 5 µm.” [0063]. Claim 19: the thickness of the alpha particle shield is approximately 5 micrometers. “The second UBM layers 1305 may be formed to have a thickness of between about 0.7 µm and about 10 µm, such as about 5 µm.” [0063]. Claim 20: the thickness of the alpha particle shield is approximately 8 micrometers ([0063]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 21 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin in evidence of Keser, US 2019/0206800 A1. Alternatively, claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Keser. Lin discloses metallization layers 211 disposed in the substrate (See FIG. 10D). Another name for such metallizations is traces. See Keser, [0025], FIG. 1, traces 152. Thus Lin discloses that the substrate further comprises a plurality of traces disposed therein. Alternatively, it was well-known in the art to have traces to distribute electrical signals, as shown by Keser, and it would have been obvious to have had them in Lin for this purpose. Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kato, US 2015/0371984 A1 in view of Farooq, US 2009/0039515 A1, and Fujimori, US 2020/0303290 A1. Claim 11: Kato discloses a substrate (10); a plurality of electrical contacts (44) disposed on an outer surface of the substrate; a solder resist (42 and 46) disposed on the outer surface of the substrate and at least partially surrounding the plurality of electrical contacts. Kato is designed to be attached to a die, but does not show the die. Fujimori shows a semiconductor die (20) disposed above, in a direction, the substrate and electrically coupled to the substrate via the plurality of electrical contacts 30. PNG media_image5.png 480 798 media_image5.png Greyscale The die intended to be attached to Kato would be similarly attached. In Kato in view of Farooq, at least a portion of the alpha particle shield would be disposed, in the direction, between the at least one edge and the semiconductor die. PNG media_image6.png 378 632 media_image6.png Greyscale Claim 11 also recites an alpha particle shield disposed between at least a portion of the solder resist and at least a portion of the semiconductor die. Kato does not disclose an alpha particle shield. However, these were known in the art. See Farooq, FIG. 2, alpha particle shield (104, containing alpha blocking material 108, [0020]) disposed as the outer layer of the device. PNG media_image7.png 504 422 media_image7.png Greyscale It would have been obvious to have had such a layer to protect the device from soft errors caused by alpha radiation (Farooq [0004]). In Kato in view of Farooq, the alpha shielding layer 104 would be disposed between at least a portion of the solder resist and at least a portion of the semiconductor die. Claim 12: the solder resist includes an opening exposing the plurality of electrical contacts. In Kato in view of Farooq, the alpha particle shield is disposed at an edge of the opening. PNG media_image8.png 378 630 media_image8.png Greyscale Claim 13: Kato discloses a polyimide layer disposed on the outer surface of the substrate and surrounding the plurality of electrical contacts: PNG media_image9.png 378 630 media_image9.png Greyscale In Kato in view of Farooq, the alpha particle shield would be coupled to the polyimide layer. Claim 14: In Kato in view of Farooq, at least a portion of the polyimide layer is disposed between the solder resist and the alpha particle shield. Claim 15: the alpha particle shield includes a first substantially planar portion (on top of 46) and a second substantially planar portion (on sidewall of 46) extending at an angle with respect to the first substantially planar portion. Claim 16: the first substantially planar portion (on top of 46) extends substantially parallel to the outer surface of the substrate, and wherein the second substantially planar (on sidewall of 46) portion extends, from an edge of the first substantially planar portion, toward the plurality of electrical contacts. Claim 17: the alpha particle shield is a copper shield (Farooq [0020], [0028]). Note: given the technical context, which is blocking alpha (α) particles, the important aspect of copper is its nucleus, rather than its chemical or electrical properties. Therefore the examiner interprets “copper shield” to be a shield that contains copper in any form, including copper compounds. Claim 18: in Kato in view of Farooq, at least a portion of the alpha particle shield is disposed, in a direction, above the solder resist.. Claims 18-20: Farooq at [0028] discloses that the thickness of the alpha particle shield is determined by the composition of the layer and the energy of the potential alpha particles. This, together with the blocking properties of other layers, and the level of risk acceptable, would allow one of skill in the art to determine the desired thickness of the alpha particle shield. Thus the thickness of the alpha particle shield is a result-effective variable, and it would have been within ordinary skill in the art to determine. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PETER BRADFORD/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Nov 13, 2023
Application Filed
Jan 20, 2026
Non-Final Rejection mailed — §102, §103
Mar 02, 2026
Interview Requested
Apr 20, 2026
Response Filed
Jul 01, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
80%
Grant Probability
85%
With Interview (+4.2%)
2y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 750 resolved cases by this examiner. Grant probability derived from career allowance rate.

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