DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed December 22, 2025 has been entered. Claims 2-6, 8-10, 12-17, and 20-21 remain pending in this application. Claims 2, 5, 10, 12, and 17 have been amended, adding no new matter. No claims have been added.
Claim Objections
Claim 17 objected to because of the following informalities:
Claim 17 is tagged “Previously Presented,” but is specifically amended and included in the list of amended claims identified by Applicant (Applicant’s Response, Page 8, ¶1). Claim will be treated as Amended.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 5-6, 8-10, 12-17, and 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 5,796,669 to Takashi Araki, et al. (hereafter Araki) in view of US 5,995,404 to Masayuki Nakaumura, et al. (hereafter Nakaumura), US 20040017714 A1 to Sun Hyoung Lee, et al. (hereafter Lee), and US 9,728,245 B2 to Kuljit S. Bains (hereafter Bains).
Regarding Amended Independent Claim 2, Araki discloses a method comprising:
receiving a first command (Disclosing transmitting a first command: Araki, col.14:18)
to refresh one or more memory banks (Disclosing refreshing one or more memory banks in response to the refresh command: Araki, col.15:4-7)
of a first set of memory banks (Disclosing a first set of memory banks: Araki, Figure 9)
comprising an odd set of memory banks of a plurality of memory banks (Within the broadest reasonable interpretation, the first group of banks, Bank0 and Bank1, may be considered odd memory banks in a vertical sequencing of memory banks: Araki, Figure 9 and 10)
receiving a second command (Disclosing an alternate command to refresh either of the groups of memory banks, such that a first command will refresh one group of memory banks and a second command will refresh a second group of memory banks: Araki, col.13:65-14:10)
to refresh one or more memory banks
of a second set of memory banks
comprising an even set of memory banks of the plurality of memory banks (Within the broadest reasonable interpretation, the second group of banks, Bank2 and Bank3, may be construed to comprise the even set of memory banks: Araki, Figure 9 and 10);
capturing a first row address (Disclosing capturing a first row address from the refresh address counter/register 6c: Araki, Figure 10)
stored in a shared memory register (Disclosing a memory register capturing a memory address: Araki, Figure 1; Note, this figure discloses a single shared register with multiple counters: Araki, col.3:20-27)
based on receiving the first command (Disclosing refreshing a row of memory cells in the designated bank in response to receiving a first command: Araki, col.14:5-10);
in response to capturing the first row address,
refreshing a first row of the first set of memory banks (Disclosing refreshing a row of memory cells in the designated bank in response to receiving a first command: Araki, col.14:5-10)
associated with the first row address (Disclosing the first row associated with the first row address from the refresh address counter 6c: Araki, col.13:31-34);
in response to refreshing the first row, (Disclosing refreshing a first acting as a trigger: Araki, col.14:11)
incrementing the first row address to obtain a second row address (Disclosing incrementing the first row address in response to the activation of a refresh signal: Araki, col.14:11-14);
in response to incrementing the first row address,
refreshing a second row of the first set of memory banks
associated with the second row address (Disclosing incrementing the captured address and sequentially refreshing rows of memory cells: Araki, col.14:23-30),
capturing an additional first row address
stored in the memory register (Disclosing operating on a second memory address stored in the memory register: Araki, col.14:31-40)
based on receiving the second command (Disclosing a second command: Araki, col.14:41),
wherein the capturing the first row address and the capturing the additional first row address occur independently (Disclosing capturing the first row address for the first set of banks independently from capturing the additional first row address for the second set of banks: Araki, col.13:31-35);
in response to capturing the additional first row address,
refreshing an additional first row of the second set of memory banks
associated with the additional first row address (Disclosing refreshing an additional first row of memory cells in response to a second command: Araki, col.15:7-8)
in response to refreshing the additional first row,
incrementing the additional first row address
to obtain an additional second row address
in response to incrementing the additional first row address,
refreshing an additional second row of the second set of memory banks
associated with the additional second row address (Disclosing the 2-bank refresh operation mirroring the auto-refresh operation, thereby including corresponding steps: Araki, col.15:7); and
refreshing all memory banks
of the first set of memory banks and
the second set of memory banks
based on receiving the third command (Disclosing stepping through all four banks sequentially in response to a ΦREF signal: Araki, col.14:11-17).
Araki implies the existence of a memory register for storing the memory address (Disclosing a memory register capturing a memory address: Araki, Figure 1). Lee, however, explicitly teaches the use of a row address latch serving as a memory register (Lee, Row Address Latch 65 in Figure 1; See Also, Lee, ¶[0045]). Lee teaches the row address latch provides the row address to the row decoder 70 for further memory operations. It would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to combine the known row address latch of Lee with the memory bank management method of Araki in order to effectively hold and maintain a row address for reliable memory operations, with a reasonable expectation of success. The combination of known inventions with predictable results is obvious and not patentable.
Araki does not explicitly disclose a method wherein the odd set of memory banks comprise every other memory bank that is interleaved between memory banks of an even set of memory banks of the plurality of memory banks. Nakaumura, however, teaches a method wherein: the odd set of memory banks comprise every other memory bank that is interleaved between memory banks of an even set of memory banks of the plurality of memory banks (Teaching interleaving memory banks of even/odd numerical designations: Nakaumura, Figures 2, 3, 10, and 11). Nakaumura teaches this alignment of banks allows for the efficient coupling of cells, minimizing the length of I/O lines and reducing parasitic capacitances occurring in these lines (Nakaumura, col.11:43-49).
It would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the memory bank refreshing method of Araki with the interleaved memory banks of Nakaumura with a reasonable expectation of success. The inventions are known variants of memory bank architecture and the combination of known inventions with predictable results is obvious and not patentable.
Araki discloses a refresh of all memory banks (Disclosing the command ΦREF alternately selecting the refresh address counters, selecting each of the exemplar four memory banks in turn: Araki, col.14:11-17) in response to a combination of signals (Disclosing an additional command ΦREF: Araki, col.14:11). It does not, however, disclose performing this operation in response to a single command that is different from the first and second commands. Bains, however, teaches separate commands for refreshing all banks, specific banks, or specific portions of banks (Bains, col.5:16-35). Bains teaches this method allows the memory controller to more carefully control access timing of issued commands (Bains, col.5:7-15).
Therefore, it would have been obvious to one having ordinary skill in the art to combine the all bank refresh logic of Bains with the alternating bank refresh logic of Araki, the separate command helping reduce required circuitry and lowering production costs. The inventions are known variants of DRAM memory refresh operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 5 and the substantially equivalent electronic device of claim 12, Araki discloses the method of claim 2, wherein
the shared memory register (Disclosing a memory register capturing a memory address: Araki, Figure 1; Note, this figure discloses a single shared register with multiple counters: Araki, col.3:20-27; See Also Lee, Row Address Latch 65 in Figure 1)
stores the first row address (Teaching Row Address Latch 65 latching the row address: Lee, ¶[0045])
in response to receiving the first row address (Teaching the Row Address Latch 65 receiving the first row address from the address input unit: Lee, ¶[0045]).
from an output of a multiplexer (Disclosing the first row address coupled to the output of multiplexer 11: Araki, Figure 10)
via a shared address path (Disclosing the output of multiplexer 11 shared by both sets/groups: Araki, Figure 10).
Regarding Claim 6, the substantially equivalent electronic device of claim 15, and the tangible media of claim 20, Araki discloses the method of claim 2, comprising
activating a third row
of the second set of memory banks
based on refreshing
the first row of the first set of memory banks,
the second row of the first set of memory banks,
or both (Disclosing repeat sequential selection of one of the four banks and refresh for a row of memory cells in the selected bank: Araki, col.14:27-29).
Regarding Claim 8, the substantially equivalent electronic device of claim 14, and the tangible media of claim 21, Araki discloses the method of claim 2, comprising
incrementing a third row address
stored in a first bank refresh counter
corresponding to the first set of memory banks (Disclosing incrementing/counting 6c, associated with the first group of Bank 0 and Bank1 in Figure 9: Araki, Figure 10), or
incrementing a fourth row address
stored in a second bank refresh counter
corresponding to a second set of memory banks (Disclosing incrementing/counting 6d, associated with the second group of Bank 2 and Bank 3 in Figure 9: Araki, Figure 10)
based on incrementing the first row address (Disclosing ‘to repeat sequential selection of one of the four banks and a refresh for a row of memory cells in the selected bank’: Araki, col.14:27-29; See Also ‘counting is performed so that the two banks Bank0 and Bank1 may be alternately refreshed in the first group: Araki, col.13:40-43).
Regarding Claim 9, Araki discloses the method of claim 8, wherein
the first bank refresh counter
comprises an odd bank refresh counter (Disclosing one of 6c and 6d, depending on the designation and/or numbering of the memory banks: Araki, Figure 10) and
the second bank refresh counter
comprises an even bank refresh counter (Disclosing the other of 6c and 6d, depending on the designation and/or numbering of the memory banks: Araki, Figure 10).
Regarding Amended Claim 10, Araki discloses an electronic device, comprising:
a first set of memory banks (Teaching a first set of memory banks: Nakaumura, Figure 10)
including memory bank control circuitry configured to:
receive
a first command (Disclosing transmitting a first command: Araki, col.14:18) to refresh one or more memory banks within the first set of memory banks (Disclosing refreshing one or more memory banks in response to the refresh command: Araki, col.15:4-7),
a second command (Disclosing an alternate command to refresh either of the groups of memory banks, such that a first command will refresh one group of memory banks and a second command will refresh a second group of memory banks: Araki, col.13:65-14:10) to refresh one or more memory banks within the second set of memory banks (Within the broadest reasonable interpretation, the second group of banks, Bank2 and Bank3, may be construed to comprise the even set of memory banks: Araki, Figure 9 and 10), and
capture a first row address (Disclosing capturing a first row address from the refresh address counter/register 6c: Araki, Figure 10)
stored in a shared memory register (Disclosing a memory register capturing a memory address: Araki, Figure 1; Note, this figure discloses a single shared register with multiple counters: Araki, col.3:20-27)
based on receiving the first command (Disclosing refreshing a row of memory cells in the designated bank in response to receiving a first command: Araki, col.14:5-10);
in response to capturing the first row address,
refresh a first row of the first set of memory banks associated with the first row address (Disclosing refreshing a row of memory cells in the designated bank in response to receiving a first command: Araki, col.14:5-10);
in response to refreshing the first row (Disclosing refreshing a first acting as a trigger: Araki, col.14:11),
increment the first row address to obtain a second row address (Disclosing incrementing the first row address in response to the activation of a refresh signal: Araki, col.14:11-14);
in response to incrementing the first row address,
refresh a second row of the first set of memory banks associated with the second row address (Disclosing incrementing the captured address and sequentially refreshing rows of memory cells: Araki, col.14:23-30)
capture an additional first row address
stored in the shared memory register (Disclosing operating on a second memory address stored in the memory register: Araki, col.14:31-40)
wherein the capturing the first row address and the capturing the additional first row address occur independently (Disclosing capturing the first row address for the first set of banks independently from capturing the additional first row address for the second set of banks: Araki, col.13:31-35);
based on receiving the second command;
in response to capturing the additional first row address,
refresh an additional first row of the second set of memory banks associated with the additional first row address;
in response to refreshing the additional first row,
increment the additional first row address to obtain an additional second row address;
in response to incrementing the additional first row address,
refresh an additional second row of the second set of memory banks
associated with the additional second row address (Disclosing the 2-bank refresh operation mirroring the auto-refresh operation, thereby including corresponding steps: Araki, col.15:7); and
refresh all memory banks
of the first set of memory banks and
the second set of memory banks
based on receiving the third command (Disclosing stepping through all four banks sequentially in response to a ΦREF signal: Araki, col.14:11-17).
Araki implies the existence of a memory register for storing the memory address (Disclosing a memory register capturing a memory address: Araki, Figure 1). Lee, however, explicitly teaches the use of a row address latch serving as a memory register (Lee, Row Address Latch 65 in Figure 1; See Also, Lee, ¶[0045]). Lee teaches the row address latch provides the row address to the row decoder 70 for further memory operations. It would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to combine the known row address latch of Lee with the memory bank management method of Araki in order to effectively hold and maintain a row address for reliable memory operations, with a reasonable expectation of success. The combination of known inventions with predictable results is obvious and not patentable.
Araki discloses a refresh of all memory banks (Disclosing the command ΦREF alternately selecting the refresh address counters, selecting each of the exemplar four memory banks in turn: Araki, col.14:11-17) in response to a combination of signals (Disclosing an additional command ΦREF: Araki, col.14:11). It does not, however, disclose performing this operation in response to a single command that is different from the first and second commands. Bains, however, teaches separate commands for refreshing all banks, specific banks, or specific portions of banks (Bains, col.5:16-35). Bains teaches this method allows the memory controller to more carefully control access timing of issued commands (Bains, col.5:7-15).
Therefore, it would have been obvious to one having ordinary skill in the art to combine the all bank refresh logic of Bains with the alternating bank refresh logic of Araki, the separate command helping reduce required circuitry and lowering production costs. The inventions are known variants of DRAM memory refresh operations and the combination of known inventions with predictable results is obvious and not patentable.
Araki does not explicitly disclose an electronic device wherein a first set of memory banks comprising an odd set of memory banks, wherein the odd set of memory banks comprises every other memory bank that is interleaved between memory banks of an even set of memory banks of the plurality of memory banks; a second set of memory banks coupled to the first set of memory bank, where in the second set of memory banks comprises the even set of memory banks interleaved between the odd set of memory banks; and memory bank control circuitry coupled to the first set of memory banks and the second set of memory banks. Nakaumura, however, teaches an electronic device comprising:
an odd set of memory banks of a plurality of memory banks,
wherein the odd set of memory banks comprises every other memory bank that is interleaved between memory banks of an even set of memory banks of the plurality of memory banks (Teaching interleaved banks of even and odd memory banks within a first group of memory banks: Nakaumura, Figure 10);
a second set of memory banks (Teaching a first set of memory banks: Nakaumura, Figure 10)
coupled to the first set of memory banks,
wherein the second set of memory banks comprises the even set of memory banks interleaved between the odd set of memory banks (Teaching interleaved banks of even and odd memory banks within a first group of memory banks: Nakaumura, Figure 10); and
memory bank control circuitry
coupled to the first set of memory banks
and the second set of memory banks (Teaching memory bank circuitry, such as peripheral circuits coupled to the first and second second set of memory banks: Nakaumura, Figure 3).
Nakaumura teaches this alignment of banks allows for the efficient coupling of cells, minimizing the length of I/O lines and reducing parasitic capacitances occurring in these lines (Nakaumura, col.11:43-49).
It would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the memory bank refreshing device logic of Araki with the interleaved memory banks of Nakaumura with a reasonable expectation of success. The inventions are known variants of memory bank architecture and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 13, Araki discloses the electronic device as in claim 12 wherein
an even bank refresh counter (Disclosing one of 6c and 6d, depending on the designation and/or numbering of the memory banks: Araki, Figure 10) and
an odd bank refresh counter (Disclosing the other of 6c and 6d, depending on the designation and/or numbering of the memory banks: Araki, Figure 10)
are coupled to respective inputs of the multiplexer (Disclosing the inputs of 11, depending on the designation of the memory banks: Araki, Figure 10).
Regarding Claim 16, Araki discloses the electronic device of claim 10, wherein
the second set of memory banks
is coupled to the first set of memory banks
via a shared address path (Disclosing an output of 11, shared by both groups of memory cells: Araki, Figure 10).
Regarding Amended Independent Claim 17, Araki discloses
Tangible, non-transitory, computer-readable media (Disclosing a tangible synchronous semi-conductor memory device: Araki, col.3:55-57),
comprising instructions that,
when executed, cause one or more processors to:
receive a first command (Disclosing transmitting a first command: Araki, col.14:18)
to refresh one or more memory banks (Disclosing refreshing one or more memory banks in response to the refresh command: Araki, col.15:4-7)
of a first set of memory banks comprising (Disclosing a first set of memory banks: Araki, Figure 9)
an odd set of memory banks of a plurality of memory banks (Within the broadest reasonable interpretation, the first group of banks, Bank0 and Bank1, may be considered odd memory banks in a vertical sequencing of memory banks: Araki, Figure 9 and 10; See Also, Araki, col.13-11),
receive a second command (Disclosing an alternate command to refresh either of the groups of memory banks, such that a first command will refresh one group of memory banks and a second command will refresh a second group of memory banks: Araki, col.13:65-14:10)
to refresh one or more memory banks
of a second set of memory banks
comprising an even set of memory banks (Within the broadest reasonable interpretation, the second group of banks, Bank2 and Bank3, may be construed to comprise the even set of memory banks: Araki, Figure 9 and 10), and
capture a first row address (Disclosing capturing a first row address from the refresh address counter/register 6c: Araki, Figure 10)
stored in a shared memory register (Disclosing a memory register capturing a memory address: Araki, Figure 1; Note, this figure discloses a single shared register with multiple counters: Araki, col.3:20-27)
based on receiving the first command (Disclosing refreshing a row of memory cells in the designated bank in response to receiving a first command: Araki, col.14:5-10);
in response to capturing the first row address,
refresh a first row of the first set of memory banks (Disclosing refreshing a row of memory cells in the designated bank in response to receiving a first command: Araki, col.14:5-10)
associated with the first row address (Disclosing the first row associated with the first row address from the refresh address counter 6c: Araki, col.13:31-34);
in response to refreshing the first row (Disclosing refreshing a first acting as a trigger: Araki, col.14:11),
increment the first row address to obtain a second row address (Disclosing incrementing the first row address in response to the activation of a refresh signal: Araki, col.14:11-14);
in response to incrementing the first row address,
refresh a second row of the first set of memory banks associated with the second row address (Disclosing incrementing the captured address and sequentially refreshing rows of memory cells: Araki, col.14:23-30)
capture an additional first row address stored in the shared memory register (Disclosing operating on a second memory address stored in the memory register: Araki, col.14:31-40) based on receiving the second command (Disclosing a second command: Araki, col.14:41)
wherein the capturing the first row address and the capturing the additional first row address occur independently (Disclosing capturing the first row address for the first set of banks independently from capturing the additional first row address for the second set of banks: Araki, col.13:31-35);
in response to capturing the additional first row address,
refresh an additional first row of the second set of memory banks
associated with the additional first row address (Disclosing refreshing an additional first row of memory cells in response to a second command: Araki, col.15:7-8);
in response to refreshing the additional first row,
increment the additional first row address to obtain an additional second row address;
in response to incrementing the additional first row address,
refresh an additional second row of the second set of memory banks associated with the additional second row address (Disclosing the 2-bank refresh operation mirroring the auto-refresh operation, thereby including corresponding steps: Araki, col.15:7).
Araki implies the existence of a memory register for storing the memory address (Disclosing a memory register capturing a memory address: Araki, Figure 1). Lee, however, explicitly teaches the use of a row address latch serving as a memory register (Lee, Row Address Latch 65 in Figure 1; See Also, Lee, ¶[0045]). Lee teaches the row address latch provides the row address to the row decoder 70 for further memory operations. It would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to combine the known row address latch of Lee with the memory bank management method of Araki in order to effectively hold and maintain a row address for reliable memory operations, with a reasonable expectation of success. The combination of known inventions with predictable results is obvious and not patentable.
Araki discloses a refresh of all memory banks (Disclosing the command ΦREF alternately selecting the refresh address counters, selecting each of the exemplar four memory banks in turn: Araki, col.14:11-17) in response to a combination of signals (Disclosing an additional command ΦREF: Araki, col.14:11). It does not, however, disclose performing this operation in response to a single command that is different from the first and second commands. Bains, however, teaches separate commands for refreshing all banks, specific banks, or specific portions of banks (Bains, col.5:16-35). Bains teaches this method allows the memory controller to more carefully control access timing of issued commands (Bains, col.5:7-15).
Therefore, it would have been obvious to one having ordinary skill in the art to combine the all bank refresh logic of Bains with the alternating bank refresh logic of Araki, the separate command helping reduce required circuitry and lowering production costs. The inventions are known variants of DRAM memory refresh operations and the combination of known inventions with predictable results is obvious and not patentable.
Araki does not explicitly disclose tangible, non-transitory, computer-readable media wherein the odd set of memory banks comprises every other memory bank that is interleaved between memory banks of an even set of memory banks of the plurality of memory banks. Nakaumura, however, teaches a device wherein the odd set of memory banks comprises every other memory bank that is interleaved between memory banks of an even set of memory banks of the plurality of memory banks (Teaching interleaving memory banks of even/odd numerical designations: Nakaumura, Figures 2, 3, 10, and 11).
Nakaumura teaches this alignment of banks allows for the efficient coupling of cells, minimizing the length of I/O lines and reducing parasitic capacitances occurring in these lines (Nakaumura, col.11:43-49).
It would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the memory bank refreshing device logic of Araki with the interleaved memory banks of Nakaumura with a reasonable expectation of success. The inventions are known variants of memory bank architecture and the combination of known inventions with predictable results is obvious and not patentable.
Response to Arguments
Applicant's arguments filed December 22, 2025 have been fully considered but they are not persuasive.
Applicant argues prior art Araki discloses only, “continuously incremented refresh address counters within a single refresh control flow.” (Applicant’s response, Page 9, ¶4). While it is true Araki discloses a single component comprising individual counters (Araki, Figure 1), it is unclear how this differs from applicant’s amended language requiring a ‘shared memory register.’ (Amended Claim 1).
The prior office action stated, “Araki implies the existence of a memory register for storing the memory address (Disclosing a memory register capturing a memory address: Araki, Figure 1), but the disclosure is not explicit.” Based on the clarification of the amended claims, this statement is no longer accurate. A memory register as disclosed by the claims may be found within Araki, specifically Figure 1. The bolstering disclosure provided by Lee remains to support this teaching and to ensure the record remains clear.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies. Specifically, applicant implies the statement, “wherein the capturing the first row address and the capturing the additional first row address occur independently,” requires the first row address and the additional row address may not only occur independently from each other, but from other addresses that have come before. As a result, Applicant suggests the sequential operation of Araki precludes the independent capture of addresses as disclosed here (Applicant’s Response, Page 10, ¶1). This limitation is not stated in the claim, however. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The captured first row address of Araki need not be independent of what came before, it only needs to be independent of the additional first row address capture. Araki expressly discloses incrementing the first address counter of the second address counter (Araki, col.13:31-35). There is no requirement the first address counter and the second address counter correspond, in fact given the described method of Araki, it is unlikely they will.
Finally, Applicant argues the disclosed prior art fails to teach a third command for a full refresh of all memory banks (Applicant’s response, Page 11, ¶2). Applicant argues this is because the sequential refresh of Araki does not include a full refresh and Bains teaches a full refresh but with a different architecture. However, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2023/0154520 A1 to Atsushi Hatakeyama: Teaching a multi-bank DRAM refresh system where sets of banks may be refreshed independently in response to a first and second refresh command.
US 2022/0406368 A1 to Sang-Hoon Jung, et al.: Teaching a DRAM memory refresh operation making use of an address register.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 01/09/2026
Prosecution Insights