DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to Amendments/Remarks filed on May 20, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 4-7, 9, 12-13, and 28-29 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2020/0266060 A1 to Cheng et al. (“Cheng”) in view of U.S. Patent Application Publication No. 2024/0222483 A1 to Naylor et al. (“Naylor”). As to claim 1, although Cheng discloses a field effect transistor comprising: a substrate (100); a channel layer (112, 114, 116) on the substrate (100); a first composite electrode layer (140, 150, 190) connected to a first side of the channel layer (112, 114, 116); a second composite electrode layer (140, 150, 190) connected to a second side of the channel layer (112, 114, 116); a gate electrode layer (174) between the first composite electrode layer (140, 150, 190) and the second composite electrode layer (140, 150, 190); and a high-k gate dielectric layer (172) between the channel layer (112, 114, 116) and the gate electrode layer (174), wherein at least one of the first (140, 150, 190) and second (140, 150, 190) composite electrode layers comprises a contact resistance reducing layer (140) in contact with the channel layer (112, 114, 116), and a conductive layer (190) on the contact resistance reducing layer (140) and spaced apart from the channel layer (112, 114, 116), wherein a length of the channel layer (112, 114, 116) is longer than the gate electrode layer (174) in a horizontal direction, the horizontal direction parallel to an upper surface of the substrate (100), and wherein the first composite electrode layer (140, 150, 190) and the second composite electrode layer (140, 150, 190) are disposed on the channel layer (112, 114, 116) such that the first composite electrode layer (140, 150, 190) and the second composite electrode layer (140, 150, 190) are isolated from each other and separated from the gate electrode layer (174) (See Fig. 1, ¶ 0002, ¶ 0036-¶ 0041, ¶ 0061-¶ 0064, ¶ 0086, ¶ 0087), Cheng does not further disclose wherein the channel layer including a transition metal dichalcogenide (TMD). However, Naylor does disclose wherein the channel layer including a transition metal dichalcogenide (TMD) (See Fig. 2, Fig. 6, ¶ 0021, ¶ 0023, ¶ 0038, ¶ 0044, ¶ 0046, ¶ 0100, ¶ 0101).
In view of teaching Naylor, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Cheng to have wherein the channel layer including a transition metal dichalcogenide (TMD) because the TMD provides high charge-carrier mobilities and high conductivity while being a thin layer (See ¶ 0021, ¶ 0038). As to claim 2, Cheng further discloses wherein the contact resistance reducing layer (140) comprises silicide (See ¶ 0061-¶ 0064) (Notes: the limitation “silicide” is defined as a compound of two elements, one of which is silicon by Dictionary.com). As to claim 4, Cheng discloses further comprising: a low-k dielectric layer (interfacial silicon oxide layer) between the high-k gate dielectric layer (172) and the channel layer (112, 114, 116) (See ¶ 0037). As to claim 5, Cheng further discloses wherein the contact resistance reducing layer (140) and the low-k dielectric layer (interfacial silicon oxide layer) share an elemental component (silicon) (See ¶ 0037, ¶ 0061-¶ 0064). As to claim 6, Cheng further discloses wherein the low-k dielectric layer (interfacial silicon oxide layer) comprises an oxide layer including at least one of Si and Ge (See ¶ 0037). As to claim 7, Cheng further discloses wherein the conductive layer (190) includes one or more types of metal (See ¶ 0086) As to claim 9, Cheng in view of Naylor further discloses wherein the channel layer (112, 114, 116) includes a semiconductor material having a band gap of 0.1 eV or more (See Naylor ¶ 0046 and [0076] of the Specification). As to claim 12, Cheng further discloses wherein the channel layer (112, 114, 116) comprises: a plurality of sub-channel layers (112, 114, 116) sequentially stacked in a direction perpendicular to a surface of the substrate (100) and spaced apart from each other in the perpendicular direction, and the high-k gate dielectric layer (172) and the gate electrode layer (174) surround each of the plurality of sub-channel layers (112, 114, 116) (See Fig. 1). As to claim 13, Cheng discloses further comprising: a plurality of insulating layers (138) connecting the first composite electrode layer (140, 150, 190) and the second composite electrode layer (140, 150, 190) to each other, the plurality of insulating layers (138) sequentially stacked in a direction perpendicular to a surface of the substrate (100) and spaced apart from each other, wherein the channel layer (112, 114, 116) has a three-dimensional structure surrounding the plurality of insulating layers (138), and the high-k gate dielectric layer (172) and the gate electrode layer (174) surround each of the plurality of insulating layers (138) on the channel layer (112, 114, 116) (See Fig. 1) (Notes: the gate dielectric layer and the gate electrode layer of the gate all around structure sandwich and surround the insulating layers on the channel layer). As to claim 28, Cheng in view of Naylor discloses an electronic device comprising: a switching element (625); and a data storage (650) connected to the switching element (625), wherein the switching element (625) comprises the field effect transistor of claim 1 (See Cheng ¶ 0087 and Naylor Fig. 6, ¶ 0101). As to claim 29, Cheng in view of Naylor discloses an electronic apparatus comprising the transistor of claim 1 (See Cheng ¶ 0087 and Naylor Fig. 6, ¶ 0101).
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2020/0266060 A1 to Cheng et al. (“Cheng”) and U.S. Patent Application Publication No. 2024/0222483 A1 to Naylor et al. (“Naylor”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2022/0199797 A1 to Naskar et al. (“Naskar”). The teachings of Cheng and Naylor have been discussed above.
As to claim 8, although Cheng discloses the conductive layer (190), Cheng and Naylor do not further disclose wherein the conductive layer includes at least one of Ti, Ni, Mo, W, Co, Pt, Hf, Ta, Cu, Cr, Yb, Er, or Pd. However, Naskar does disclose wherein the conductive layer (440B, 442B) includes at least one of Ti, Ni, Mo, W, Co, Pt, Hf, Ta, Cu, Cr, Yb, Er, or Pd (See ¶ 0138). In view of teaching Naskar, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Cheng to have wherein the conductive layer includes at least one of Ti, Ni, Mo, W, Co, Pt, Hf, Ta, Cu, Cr, Yb, Er, or Pd because Ti, Ni, Mo, W, Co, Pt, Hf, Ta, Cu, Cr, Yb, Er, and Pd are known metal materials to provide low resistivity for the conductive layer (See ¶ 0138).
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2020/0266060 A1 to Cheng et al. (“Cheng”) and U.S. Patent Application Publication No. 2024/0222483 A1 to Naylor et al. (“Naylor”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2013/0295732 A1 to Wu et al. (“Wu”). The teachings of Cheng and Naylor have been discussed above. As to claim 10, although Cheng and Naylor do not further disclose wherein the contact resistance reducing layer includes two different types of metal and at least one of Si or Ge, Cheng in view of Wu further discloses wherein the contact resistance reducing layer (140/Wu ¶ 0045) includes two different types of metal and at least one of Si or Ge (See Wu ¶ 0045 and Claim 5), where the contact resistance reducing layer of a metal silicide comprising a compound of silicon and one or metals is commonly provided to reduce the contact resistance.
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID CHEN/Primary Examiner, Art Unit 2815
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