DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment/Restriction
Applicant's election with traverse of Group 1, Species VII, Sub 1, and Claims 1-2, 4-10, 12-13 and 28-29 in the reply filed on February 02, 2026 is acknowledged. The traversal is on the ground(s) that “an election of species does not reduce the burden on the Examiner…could not properly exclude the non-elected species due to claim 1 being generic to all of the listed species...Applicants submit that the search and examination of all the claims may be made without serious burden.” This is not found persuasive because as set forth in the Restriction Requirement on January 23, 2026, different search queries are required and prior art applicable to one species would not likely be applicable to another species. Although the independent claim may be generic, the species may comprise structural differences that are mutually exclusive. Lastly, Group II requires specific sequential steps that may be narrower than Group I.
The requirement is still deemed proper and is therefore made FINAL.
Specification
The title of the invention is broad and not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claim 12, the limitation “the gate insulating layer” lacks sufficient antecedent basis. Thus, the limitation renders the claim indefinite and clarification is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2016/0020305 A1 to Obradovic et al. (“Obradovic”).
As to claim 1, Obradovic discloses a field effect transistor comprising: a substrate (107); a channel layer (101, 102) on the substrate (107), the channel layer (101, 102) including a two-dimensional semiconductor (nanosheet); a first composite electrode layer (111, 109s1, 109s2, 109e) connected to a first side of the channel layer (101, 102); a second composite electrode layer (111, 109d) connected to a second side of the channel layer (101, 102); a gate electrode layer (115) between the first composite electrode layer (111, 109s1, 109s2, 109e) and the second composite electrode layer (111, 109d); and a high-k gate dielectric layer (110) between the channel layer (101, 102) and the gate electrode layer (115), wherein at least one of the first (111, 109s1, 109s2) and second (111, 109d) composite electrode layers comprises a contact resistance reducing layer (109s1, 109s2, 109d, 109e) in contact with the channel layer (101, 102), and a conductive layer (111) on the contact resistance reducing layer (109s1, 109s2, 109d, 109e) and spaced apart from the channel layer (101, 102) (See Fig. 1, ¶ 0046-¶ 0052) (Notes: the contact resistance reducing layer is highly doped to reduce contact resistance and the channel layer is sandwiched between source and drain composite electrode layers).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 7-9, 12-13, and 28-29 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2022/0199797 A1 to Naskar et al. (“Naskar”) in view of U.S. Patent Application Publication No. 2016/0020305 A1 to Obradovic et al. (“Obradovic”).
As to claim 1, although Naskar discloses a field effect transistor comprising: a substrate (102); a channel layer (104, 106, 420, 422, 424, 426) on the substrate (102), the channel layer (104, 106, 420, 422, 424, 426) including a two-dimensional semiconductor (nanowire, where the two-dimensional semiconductor is included in the three-dimension structure as recited in claim 13); a first composite electrode layer (440) connected to a first side of the channel layer (104, 106, 420, 422, 424, 426); a second composite electrode layer (442) connected to a second side of the channel layer (104, 106, 420, 422, 424, 426); a gate electrode layer (438) between the first composite electrode layer (440) and the second composite electrode layer (442); and a high-k gate dielectric layer (118, 436) between the channel layer (104, 106, 420, 422, 424, 426) and the gate electrode layer (438), wherein at least one of the first (440) and second (442) composite electrode layers comprises a conductive layer (440B, 442B) (See Fig. 1, Fig. 10, Fig. 15, ¶ 0060, ¶ 0074, ¶ 0077, ¶ 0129-¶ 0138, ¶ 0154, ¶ 0163) (Notes: the channel layer is between the S/D first and second composite electrode layers), Naskar does not further disclose wherein the at least one of the first and second composite electrode layers comprises a contact resistance reducing layer in contact with the channel layer, and the conductive layer on the contact resistance reducing layer and spaced apart from the channel layer. However, Obradovic does disclose a contact resistance reducing layer (111’) in contact with the channel layer (101’, 102’, 109s1’, 109s2’, 109e’, 109d’) (See Fig. 9, ¶ 0059, ¶ 0065, ¶ 0066). In view of teaching Obradovic, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Naskar to have wherein the at least one of the first and second composite electrode layers comprises a contact resistance reducing layer in contact with the channel layer, and the conductive layer on the contact resistance reducing layer and spaced apart from the channel layer because the contact resistance reducing layer in contact with the channel layer provides low interfacial resistivity to improve the device performance (See ¶ 0066). As to claim 2, Naskar in view of Obradovic further discloses wherein the contact resistance reducing layer (111’) comprises silicide (See Obradovic ¶ 0066). As to claim 7, Naskar further discloses wherein the conductive layer (440B, 442B) includes one or more types of metal (See ¶ 0138) As to claim 8, Naskar further discloses wherein the conductive layer (440B, 442B) includes at least one of Ti, Ni, Mo, W, Co, Pt, Hf, Ta, Cu, Cr, Yb, Er, or Pd (See ¶ 0138). As to claim 9, Naskar further discloses wherein the channel layer (104, 106, 420, 422, 424, 426) includes a semiconductor material having a band gap of 0.1 eV or more (See ¶ 0060 and evidenced by Semiconductor Band Gaps at www.hyperphysics.phy-astr.gsu.edu/hbase/Tables/Semgap.html). As to claim 12, Naskar further discloses wherein the channel layer (104, 106, 420, 422, 424, 426) comprises: a plurality of sub-channel layers (104, 106, 420, 422, 424, 426) sequentially stacked in a direction perpendicular to a surface of the substrate (102) and spaced apart from each other in the perpendicular direction, and the gate insulating layer and the gate electrode layer (438) surround each of the plurality of sub-channel layers (104, 106, 420, 422, 424, 426) (See Fig. 10). As to claim 13, Naskar discloses further comprising: a plurality of insulating layers (416) connecting the first composite electrode layer (440) and the second composite electrode layer (442) to each other, the plurality of insulating layers (416) sequentially stacked in a direction perpendicular to a surface of the substrate (102) and spaced apart from each other, wherein the channel layer (104, 106, 420, 422, 424, 426) has a three-dimensional structure (nanowire) surrounding the plurality of insulating layers (416), and the gate dielectric layer (118, 436) and the gate electrode layer (438) surround each of the plurality of insulating layers (416) on the channel layer (104, 106, 420, 422, 424, 426) (See Fig. 10, ¶ 0154) (Notes: the gate dielectric layer and the gate electrode layer of the gate all around structure sandwich and surround the insulating layers on the channel layer). As to claim 28, Naskar discloses an electronic device comprising: a switching element (1000); and a data storage (1502) connected to the switching element (1000), wherein the switching element (1000) comprises the field effect transistor of claim 1 (See Fig. 15, ¶ 0163). As to claim 29, Naskar discloses an electronic apparatus comprising the transistor of claim 1 (See Fig. 15, ¶ 0163).
Claim(s) 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2022/0199797 A1 to Naskar et al. (“Naskar”) and U.S. Patent Application Publication No. 2016/0020305 A1 to Obradovic et al. (“Obradovic”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2021/0134677 A1 to Pan et al. (“Pan”). The teachings of Naskar and Obradovic have been discussed above. As to claim 4, Naskar in view of Pan discloses further comprising: a low-k dielectric layer (332) between the high-k gate dielectric layer (118, 436/334) and the channel layer (104, 106, 420, 422, 424, 426/202, 204, 206) (See Pan Fig. 16, ¶ 0037, ¶0038) such that the low-k dielectric layer further increases adhesion between the channel layer and the high-k gate dielectric layer. As to claim 5, Naskar in view of Obradovic and Pan further discloses wherein the contact resistance reducing layer (111’) and the low-k dielectric layer (332) share an elemental component (silicon) (See Obradovic ¶ 0047, ¶ 0048, ¶ 0066 and Pan ¶ 0037). As to claim 6, Naskar in view of Pan further discloses wherein the low-k dielectric layer (332) comprises an oxide layer including at least one of Si and Ge (See Pan Fig. 16, ¶ 0037).
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2022/0199797 A1 to Naskar et al. (“Naskar”) and U.S. Patent Application Publication No. 2016/0020305 A1 to Obradovic et al. (“Obradovic”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2013/0295732 A1 to Wu et al. (“Wu”). The teachings of Naskar and Obradovic have been discussed above. As to claim 10, Naskar in view of Obradovic and Wu further discloses wherein the contact resistance reducing layer (111’/Wu ¶ 0045) includes two different types of metal and at least one of Si or Ge (See Wu ¶ 0045 and Claim 5), where the contact resistance reducing layer of a metal silicide comprising a compound of silicon and one or metals is commonly provided to reduce the contact resistance.
Conclusion
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/DAVID CHEN/Primary Examiner, Art Unit 2815