DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on April 23, 2026 is acknowledged. The requirement is still deemed proper and is therefore made FINAL.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: claim 3 and by extension, dependent claim 5, recite the limitation of removing a thicker layer of the mandrel structures selectively with respect to the spacers, with the thicker layer defined as a top layer of the thin oxide layer of the mandrel structures. However, claim 1 already states a step of "selectively removing at least a top layer of the mandrel structures." The subject matter of claim 1 is supported by Figs. 7-8 of the instant application shows top layer 4b of the mandrel structure being removed. However, no other description regarding removing yet another top layer on top of the mandrel structure, as required by claim 3. Hence, claim 3 has no antecedent basis in the specifications or the figures.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed subject matter in claim 3, as described in the objections to specifications above, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
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Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, and by extension, dependent claims 2-10, has a preamble that contains both method and device descriptions and hence, crosses two statutory classes. Furthermore, the last limitation of claim 1 is directed to a device structure (spacers) and recite a method of using said structure (spacers used as a spacing between gate structures). It is not clear whether claim 1 is a device claim or a method claim. See 2173.05 (p) (II): product and process in the same claim.
Claim 1, and by extension, dependent claims 2-10, recite the limitation of “providing a substrate consisting of a semiconductor material or comprising a top layer formed of a semiconductor material,” is found to be indefinite because it is unclear what other alternatives are intended to be encompassed by the claim. See MPEP 2173.05(h).
Claim 1, and by extension, dependent claims 2-10, recites the limitation "the height of the spacers" in the clause “wherein the oxide layer is thinner than the height of the spacers so that the spacers and the oxide layer define a topology.” There is insufficient antecedent basis for “a height” in the claim.
Claim 3 and by extension, dependent claim 5, recite the limitation of “removing said thicker layer of the mandrel structures selectively with respect to the spacers.” However, claim 1 already states a step of "selectively removing at least a top layer of the mandrel structures." It is unclear whether this is another step or is the same step in claim 1. For the purpose of compact prosecution, the examiner will treat this step in claim 3 to be the same as claim 1.
Claim 3 and by extension, dependent claim 5, has language that crosses two statutory limitations, i.e., device and method. The recitation of a mandrel having a thicker layer on top of a thin oxide layer and a thin layer of oxide on the substrate is a recitation of device structure, whereas the remainder of the claims are method steps. It is not clear whether claim 1 is a device claim or a method claim. See 2173.05 (p) (II): product and process in the same claim.
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The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 3 and 5 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 3 and by extension, dependent claim 5, recite the limitation of “removing said thicker layer of the mandrel structures selectively with respect to the spacers.” However, claim 1 already states a step of "selectively removing at least a top layer of the mandrel structures." Hence, claims 3 and 5 does not further delimit the limitations of claim 1. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4, 6-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Thomas (US 2019/0044049 A1) in view of Hutin (US 2019/0371908 A1).
Regarding claim 1, Thomas teaches a method for producing a quantum dot device (100) according to a pre-defined quantum dot device configuration (the arrangement of quantum dots 142 in Figs. 1-3, 43-45, 56-58), said configuration comprising an array of mutually parallel electrically conductive gate structures (110 & 112; see Fig. 2) separated from each other by a dielectric- filled spacing (spacing created by 114 & 134), the method comprising the steps of:
providing a substrate (102 & 104 formed from substrate 144, see ¶ [0064] and Figs. 4-6) consisting of a semiconductor material (¶ [0062]: silicon ) or comprising a top layer formed of a semiconductor material;
producing a plurality of parallel mandrel structures (111, see Fig. 12 and ¶ [0069] ) on the substrate;
producing spacers (134, Fig. 16) formed of a dielectric material (¶ [0071]: silicon nitride ) on side surfaces of the mandrel structures, said spacers having a given width (¶ [0046]: thickness of 134 is between 1 to 10 nm );
forming a thin auxiliary layer (113, see Fig. 13) on the mandrel structures and on the substrate, said auxiliary layer being thinner (¶ [0070]: thickness between 5 Angstroms and 20, which is 0.5 nm to 2 nm) than said spacer width (¶ [0046]: thickness of 134 is between 1 to 10 nm);
removing said auxiliary layer from the mandrel structures while substantially maintaining it on the substrate (Fig. 17 shows 113 removed from top of 111; see also ¶ [0074]);
selectively removing (¶ [0075]: using etching ) at least a top layer (Fig. 18 shows cavities 103 of mandrel structures 111 is formed) of the mandrel structures, wherein said removal is selective with respect to the spacers and with respect to said auxiliary layer (Fig. 18 shows spacers 134 and auxiliary layer 113 are intact);
removing said auxiliary layer from the substrate (see Fig. 23; ¶ [0080]: using wet etch) , and if any remaining portions of the mandrel structures are still present, removing said remaining portions (Fig. 18 shows no remaining mandrel structures 111);
producing an oxide layer (114, see Fig. 19 and ¶ [0076]; ¶ [0035] lists various oxide materials) in areas between the spacers, wherein the oxide layer is thinner than the height of the spacers (Fig. 19 shows the vertical width of oxide layer 114 is thinner than the vertical height of any of the spacers 134) so that the spacers and the oxide layer define a topology (the structure 222 as illustrated in Fig. 23);
filling up the areas between the spacers by depositing one or more conformal layers (another layer of 114 deposited on 222; see Fig. 24 and ¶ [0081] ) which follow said topography, and thereafter depositing a non-conformal layer (112, see Fig. 25 and ¶ [0082] ) that covers the spacers;
thinning and planarizing the non-conformal layer until structures (225; see Fig. 26 and ¶ [0083] ) are obtained, formed at least partially of the material of the non-conformal layer (Fig. 25 shows part of structure 225 still has non-conformal layer 112) and separated from each other by at least said dielectric material of the spacers (Fig. 26 shows each 112 is separated by spacers 134);
subsequent to the thinning and planarization step, producing said predefined quantum dot device configuration wherein :
the structures or portions thereof act as the gate structures of the quantum dot device (see Title, Abstract, and ¶ [0021] );
the oxide layer acts as a gate oxide layer (¶ [0035]: 114 is a gate dielectric ); and
the spacers act as at least part of said dielectric-filled spacing between the gate structures (Fig. 2 shows spacers 134 in between gate oxide layer 114 and gate conductive metal 112).
Thomas further teaches using any deposition technique such as ALD (see ¶ [0076]) for producing the oxide layer (114). However, Thomas does not teach using a thermal oxidation process of the semiconductor material of the substrate to produce said gate oxide layer.
Hutin, in the same field of invention, teaches a method for producing a quantum dot device (see Abstract) that uses a thermal oxidation process or a deposition process (¶ [0027] ) in order to form a gate oxide layer (102, see Figs. 5-6). Hence, Thomas in view of Hutin teaches using a thermal oxidation process to produce said gate oxide layer.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Hutin into the method of Thomas to substitute the deposition process of Thomas with the thermal oxidation process of Hutin for at least the purpose of substituting equivalent processes known in the art for forming oxide layers on semiconductor substrates of quantum dot devices ( Hutin ¶ [0027] ; see Hutin ¶ [0025]: substrate made of silicon 101 ), with the ordinary skilled artisan noting that Thomas’ substrate is also made of the same material (Thomas ¶ [0062]: silicon).
Regarding claim 2, the method according to claim 1, wherein said auxiliary layer is a thin layer of oxide of said semiconductor material (Thomas ¶ [0034]: 113 formed from aluminum oxide ), and wherein said layer is formed by a thermal oxidation step (Thomas in view of Hutin teaches the use of thermal oxidation step with the person of ordinary skill motivated in the same way as stated in claim 1 rejection).
Regarding claim 4, the method according to claim 1, wherein the substrate is a silicon substrate (Thomas ¶ [0062]: silicon) or comprises a top layer formed of silicon.
Regarding claim 6, the method according to claim 1, wherein the width of said mandrel structures ranges between 10 and 50 nm (¶ [0046]: gate metal 110, along the x-axis, is between 20 nm and 40 nm; note: mandrel structures 111 are then replaced by gate metal 110; see Figs. 17-21 ) and wherein the width of the spacers ranges between 4 and 30 nm (¶ [0046]: thickness of each spacer 134 ranges from 1 nm to 10 nm).
Regarding claim 7, the method according to claim 1, wherein the mandrel structures all have the same width (width of 111 in Thomas Fig. 12 are all the same; ¶ [0046]: the gate structure 110, along the x-direction, is between 20 nm to 40 nm; note: mandrel structures 111 are then replaced by gate metals 110; see Figs. 17-21 ), and wherein said mandrel structures are arranged in a regular array (Fig. 3 shows an array of gate structures that is derived from the mandrel structures of Fig. 12 arranged in an array) having a constant pitch (Fig. 12 shows all 111 having the same height; ¶ [0046]: z-height of 110 is between 40 to 75 nm ) of at least twice said width (20-40 nm, which is twice of 40-75 nm).
Furthermore, claim 7 recites a limitation of relative dimensions between the width of the mandrel structure with respect to the height of the gate structures. In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. See also MPEP § 2144.04 (IV)(A).
Regarding claim 8, the method according to claim 1, wherein the non-conformal layer is an electrically conductive layer (Thomas ¶ [0037]: 112 is made of metal ), so that the structures obtained after thinning and planarization are electrically conductive structures.
Regarding claim 10, the method according to claim 1, wherein one or more of the structures (Thomas Fig. 85) obtained after thinning and planarization are cut (Thomas ¶ [0178]: singulation process ) to form separate portions (die 452) of said structures, and wherein one or more of said portions act as said gate structures of the quantum dot device (see explanation in ¶ [0178] ).
Claim 9 is rejected under 35 USC 103 as being unpatentable over Thomas (US 2019/0044049 A1) in view of Hutin (US 2019/0371908 A1) as applied to claim 1, and further in view of Barraud (US 2020/0343435 A1).
Regarding claim 9, Thomas et al. teach the method according to claim 1, and further teach the non-conformal layer to be conductive metal (¶ [0037]: 112 is made of metal ) obtained by thinning and planarization (see Fig. 26 and ¶ [0083]). However, Thomas et al. do not teach: wherein the non-conformal layer is a non-electrically conductive layer, and wherein dopant elements are implanted in the structures, so that said structures become electrically conductive.
Barraud, in the same field of invention, teaches a method for producing a quantum dot device (see Abstract) wherein the non-conformal layer (132: is a gate; see ¶ [0032] and Fig. 35 ) is either a conductive metal (¶ [0052]: TiN) or is a non- electrically conductive layer (¶ [0052]: polysilicon ), and wherein dopant elements (¶ [0052]: polysilicon is doped ) are implanted in the structures, so that said structures become electrically conductive.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Barraud into the method of Thomas et al. to substitute the conductive metal that comprises the non-conformal layer with that of a doped polysilicon, for the equivalent purpose of forming conductive gate structures for quantum dot devices (Barraud ¶ [0052] ).
Allowable Subject Matter
Claims 3 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if rewritten to overcome the 35 U.S.C. § 112 rejections.
Regarding claims 3, no prior art of record was found to anticipate or render obvious the method according to claim 1, wherein the mandrel structures comprise a thin layer of oxide on the substrate and a thicker layer on top of the thin oxide layer, and wherein the method comprises:
removing said thicker layer of the mandrel structures selectively with respect to the spacers and with respect to the thin auxiliary layer; and
thereafter, removing the thin oxide layer of the mandrel structures and the auxiliary layer prior to the step of forming the gate oxide layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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