DETAILED ACTION
This action is responsive to the Request for Continued Examination filed February 11, 2026. Prior to entry claims 1-20 were pending. Claims 1-3, 5, 7, 9-11, 14, and 16-18 have been amended. Claims 4, 12, and 13 have been cancelled. Claims 21-23 are new. Thus, upon entry, claims 1-3, 5-11, and 14-23 are currently pending. Claims 1, 9 and 16 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 11, 2026, has been entered.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3, 5-7, 9-11, 14-19, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Darragh et al. (US 20170221573; “Darragh” – of Record) in view of Leem (US 20230120696 – of Record).
Regarding independent claim 1, Darragh discloses a control method for a memory,
the memory comprising a plurality of memory cells wherein the plurality of memory cells correspond to a plurality of transistors of the memory (Fig. 15);
the control method comprising:
based on the verification read voltage, reading the plurality of transistors to obtain a read failure count (para. 151; "The proposed failed bit count (“FBC”) or error rate method may be based on the error rate measurement, approximated by taking multiple reads and measuring the FBC and by using the optimal read thresholds." It is noted that Darragh's FBC is the same metric as defined in the instant application as read failure count (Spec. para. 31));
determining a product stage of the plurality of memory cells, wherein values of the read failure count indicates different product stages of the plurality of memory cells (Fig. 16 where it illustrates the increasing "FailedBitCount" between a block at 0 cycles and a block at 2k cycles. See also para. 3; "This application relates generally to memory devices. More specifically, this application relates to the measurement of wear endurance', 'Those measurements may be used for', 'end of life prediction, or adjustments to memory parameters'. It is noted that beginning of life and end of life are the indicated product stages in the instant application (Spec. para. 43)),
wherein a voltage is stored in the plurality of transistors (Fig. 14. See also para. 81; "FIG. 14 illustrates an exemplary 3D NAND flash". It is noted that all NAND flash memory cells necessarily store a voltage on the gate of the transistors),
and a voltage value of the voltage is equal to that of the verification read voltage (Fig. 12, where it illustrates the read level voltages for a two bit MLC memory cell),
and wherein the different product stages are associated with data processing times of the plurality of memory cells (Fig. 16, where it illustrates the increase of FBC due to wear. As noted above, product stage is a function of FBC, and wear is analogous to the data processing times of the instant application (Spec. para. 3));
selecting a first destination entry from a plurality of destination entries of the plurality of transistors based on the product stage of a memory cell of the plurality of memory cells corresponding to the first destination entry (Fig. 4: 404 NAND trade-off engine. See also para 53; "The NAND trade-off engine 404 may dynamically measure device performance and allow for adjustments to the device based on the measurements", "For example, trim parameters may be adjusted based on the wear"),
wherein the plurality of destination entries record processing parameters for data processing of the plurality of memory cells (The instant application appears to indicate the "destination entry" is part of Register 2 which is coupled to Control circuit 1 (both of Figure 1), which is tasked with the FBC control, and which appear to be analogous to Darragh's NAND trade-off engine of above),
the processing parameters comprise an offset voltage value and a program start voltage value for each destination entry (para. 125; " A trim parameter may include one or more parameters related to read operations, including a program rate, a program voltage level, a step-up voltage"),
and wherein the offset voltage value is determined based on a threshold voltage of the memory cell corresponding to the destination entry (Darragh's use of trim parameters to adjust the program voltage level necessarily imply the modification from a known start value which must be retrieved from where it is stored (i.e.: destination entry) as also evinced from para. 96; "The initial measurement could be at manufacture and/or after the first programming and results in the reference cell voltage distribution that is used for comparing with subsequent measurements for quantifying the changes in distribution.");
and programming the plurality of memory cells based on a plurality of program voltages generated from the program start voltage value and the offset voltage value (Fig. 3. See also para 52; "In operation", "during a write operation", The FIM controller 308 may determine how the received data is to be written onto the flash memory 116 optimally. And para. 51; "The FIM controller 308 may include the algorithms implementing the independent analysis of wear"),
wherein programming the plurality of memory cells is performed according to the different product stages of the memory (para. 3; "this application relates to the measurement of wear endurance", "Those measurements may be used for", "end of life prediction, or adjustments to memory parameters". It is noted that beginning of life and end of life are the indicated product stages in the instant application (Spec. para. 43)).
While Darragh discloses the control method elements above and verification read voltages, it is silent with respect to the specific metrics of product stages (beginning/end of life).
However, Leem teaches the control method comprising:
obtaining a verification read voltage from a voltage set, the voltage set including a plurality of threshold voltages corresponding to the plurality of transistors at a plurality of different programming times (Fig. 2B Voltage Register 243. See also para. 83; "the voltage register 243 may store a third read voltage table therein. The third read voltage table may be a table indicating a mapping relationship between an erase write cycle count, a reference voltage variation, and a third voltage variation"),
wherein the threshold voltages correspond to a range of voltages of the plurality of transistors at a first product stage and a second product stage (para. 84; " a difference between third voltage variations mapped to the fifth field value indicating a first erase write cycle count among the fifth field values may be greater than a difference between third voltage variations mapped to a fifth field value indicating a second erase write cycle count greater than the first erase write cycle count". It is noted that Leem's first and second erase cycle count are analogous to the first and second product stages of the instant application),
and the verification read voltage is a threshold voltage between the first product stage and the second product stage selected based on a distribution of the threshold voltages in the first product stage and the second product stage (As noted above, Leem's second erase write cycle count is greater than the first erase write cycle count which necessarily indicates the values are between the first and second product stages);
Darragh and Leem are from the same field of endeavor as applicant’s invention directed to tracking program and read threshold voltages as a function of wear. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Darrah’s trade-off engine with Leem’s verification read voltages based on program/erase cycle correlation to reduce the number of program verify loops. Doing so would improve memory performance.
Regarding claim 2, Darrah and Leem combined disclose the limitations of claim 1.
As applied, Leem further discloses wherein the selecting the first destination entry from the plurality of entries based on the product stage of the memory cell of the plurality of memory cells corresponding to the first destination entry comprises, if the read failure count is less than or equal to a first value (para. 86; "The read voltage controller 245 may select one voltage variation from the read voltage table RVT, based on the erase write cycle count EW_count and the fail bit count FBIT." It is noted that since the table entry is selected based on the fail bit count, the count is necessarily equal to a value),
selecting the first destination entry from the plurality of destination entries, the first destination entry corresponding to the first product stage of the plurality of memory cells (As noted above, Leem's read voltage table entry is based on the EW_count. It is well understood in the art that program/erase counts (EW_count) are a primary indicator of a memories product stage (i.e.: from beginning of life to end of life as described in the instant application)).
Regarding claim 3, Darragh and Leem disclose the limitations of claim 2.
As applied, Leem further discloses wherein the selecting the first destination entry from the plurality of destination entries based on the product stage of the memory cell corresponding to the first destination entry comprises, if the read failure count is greater than the value (para. 86; "The read voltage controller 245 may select one voltage variation from the read voltage table RVT, based on the erase write cycle count EW_count and the fail bit count FBIT." It is noted that since the table entry is selected based on the fail bit count, the count is necessarily greater than the initial value).
selecting a second destination entry from the plurality of destination entries, the second destination entry corresponding to the second product stage of the plurality of memory cells (As noted above, Leem's read voltage table entry is based on the EW_count. It is well understood in the art that program/erase counts (EW_count) are a primary indicator of a memories product stage (i.e.: from beginning of life to end of life as described in the instant application).
Regarding claim 5, Darragh and Leem combined disclose the limitations of claim 1.
As applied, Leem further discloses wherein a magnitude of the verification read voltage is between a first threshold voltage and a second threshold voltage, the first threshold corresponds to the plurality of transistors at first programming times, the first programming times correspond to the first product stage, and the second threshold voltage corresponds to the plurality of transistors at second programming times, the second programming times correspond to the second product stage (Fig. 2B: 243 read voltage table. See also para. 81; "In an embodiment, the voltage register 243 may store a first read voltage table therein. The first read voltage table may be a table indicating a mapping relationship between an erase write cycle count, a reference fail bit number, and a voltage variation". It is noted that the instant application appears to indicate that the first and second threshold voltages are the lower and upper bounds of a memory lifecycle range which is analogous to the values in Leem's read voltage table. All entries in the table would necessarily be within (between) the bounding range).
Regarding claim 6, Darragh and Leem combined disclose the limitations of claim 5.
As applied, Leem further discloses wherein the first programming times are one-tenth of the second programming times (Fig. 6A where it illustrates example contents of a read voltage table with a column of EW cycles at 100 and a second column at 1000).
Regarding claim 7, Darragh and Leem combined disclose the limitations of claim 1.
As applied, Darragh further discloses wherein the plurality of transistors are program selection transistors or dummy memory transistors (Fig. 15: SGD, SGS. It is noted that the instant application defines program selection transistors as TSG or BSG of Fig. 2 which are well understood in the art to be analogous to Darragh's SGD and SGS array transistors).
Regarding independent claim 9, Darragh discloses a parameter calculation method for a memory, the memory comprising
a plurality of memory cells, wherein the plurality of memory cells correspond to a plurality of transistors of the memory (Fig. 15);
the parameter calculation method comprising:
obtaining a verification read voltage according to the plurality of transistors (Fig. 12, where it illustrates the read level voltages for a two bit MLC memory cell. See also para. 76; "The three read margins (AR, BR, CR) delineate the four states. Likewise, there is a verify level (i.e. a voltage level) for establishing the lower bound for programming each state"),
a voltage is stored in the plurality of transistors (Fig. 14. See also para. 81; "FIG. 14 illustrates an exemplary 3D NAND flash". It is noted that all NAND flash memory cells necessarily store a voltage on the gate of the transistors),
and a voltage value of the voltage is equal to that of the verification read voltage (Fig. 12, where it illustrates the read level voltages for a two bit MLC memory cell);
based on the verification read voltage, reading the plurality of transistors to obtain a read failure count (para. 151; "The proposed failed bit count (“FBC”) or error rate method may be based on the error rate measurement, approximated by taking multiple reads and measuring the FBC and by using the optimal read thresholds." It is noted that Darragh's FBC is the same metric as defined in the instant application as read failure count (Spec. para. 31));
determining a product stage for the plurality of memory cells of the memory, wherein product stages are associated with data processing times of the plurality of memory cells (Fig. 16 where it illustrates the increasing "FailedBitCount" between a block at 0 cycles and a block at 2k cycles. See also para. 3; "This application relates generally to memory devices. More specifically, this application relates to the measurement of wear endurance', 'Those measurements may be used for', 'end of life prediction, or adjustments to memory parameters'. It is noted that beginning of life and end of life are the indicated product stages in the instant application (Spec. para. 43));
and obtaining a plurality of corresponding destination entries based on the product stages for the plurality of memory cells (Fig. 4: 404 NAND trade-off engine. See also para 53; "The NAND trade-off engine 404 may dynamically measure device performance and allow for adjustments to the device based on the measurements", "For example, trim parameters may be adjusted based on the wear");
wherein the plurality of corresponding destination entries record processing parameters for data processing of the plurality of memory cells (The instant application appears to indicate the "destination entry" is part of Register 2 which is coupled to Control circuit 1 (both of Figure 1), which is tasked with the FBC control, and which appear to be analogous to Darragh's NAND trade-off engine of above),
the processing parameters comprising an offset voltage value and a program start voltage value for each destination entry (para. 125; " A trim parameter may include one or more parameters related to read operations, including a program rate, a program voltage level, a step-up voltage"),
and wherein the offset voltage value is determined based on a threshold voltage of the memory cell corresponding to the destination entry (Darragh's use of trim parameters to adjust the program voltage level necessarily imply the modification from a known start value which must be retrieved from where it is stored (i.e.: destination entry) as also evinced from para. 96; "The initial measurement could be at manufacture and/or after the first programming and results in the reference cell voltage distribution that is used for comparing with subsequent measurements for quantifying the changes in distribution.");
and programming the plurality of memory cells based on a plurality of program voltages generated from the program start voltage value and the offset voltage value (Fig. 3. See also para 52; "In operation", "during a write operation", The FIM controller 308 may determine how the received data is to be written onto the flash memory 116 optimally. And para. 51; "The FIM controller 308 may include the algorithms implementing the independent analysis of wear"),
wherein programming the plurality of memory cells is performed according to the product stages of the memory (para. 3; "this application relates to the measurement of wear endurance", "Those measurements may be used for", "end of life prediction, or adjustments to memory parameters". It is noted that beginning of life and end of life are the indicated product stages in the instant application (Spec. para. 43)).
While Darragh discloses the parameter calculation method elements above and verification read voltages, it is silent with respect to the specific metrics of product stages (beginning/end of life).
However, Leem teaches the parameter calculation method comprising:
obtaining a verification read voltage from a voltage set, the voltage set including a plurality of threshold voltages corresponding to the plurality of transistors at a plurality of different programming times (Fig. 2B Voltage Register 243. See also para. 83; "the voltage register 243 may store a third read voltage table therein. The third read voltage table may be a table indicating a mapping relationship between an erase write cycle count, a reference voltage variation, and a third voltage variation"),
wherein the threshold voltages correspond to a range of voltages of the plurality of transistors at a first product stage and a second product stage (para. 84; " a difference between third voltage variations mapped to the fifth field value indicating a first erase write cycle count among the fifth field values may be greater than a difference between third voltage variations mapped to a fifth field value indicating a second erase write cycle count greater than the first erase write cycle count". It is noted that Leem's first and second erase cycle count are analogous to the first and second product stages of the instant application),
and the verification read voltage is a threshold voltage between the first product stage and the second product stage selected based on a distribution of the threshold voltages in the first product stage and the second product stage (As noted above, Leem's second erase write cycle count is greater than the first erase write cycle count which necessarily indicates the values are between the first and second product stages);
Darragh and Leem are from the same field of endeavor as applicant’s invention directed to tracking program and read threshold voltages as a function of wear. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Darrah’s trade-off engine with Leem’s verification read voltages based on program/erase cycle correlation to reduce the number of program verify loops. Doing so would improve memory performance.
Regarding claim 10, Darragh and Leem combined disclose the limitations of claim 9.
As applied, Leem further discloses wherein obtaining the plurality of corresponding entries based on the product stages for the plurality of memory cells comprises, if the read failure count is less than or equal to a first value, determining that the corresponding plurality of memory cells are in the first product stage, and obtaining a first destination entry according to the first product stage (Fig. 6A. It is noted that Leem's read voltage table entry is based on the EW_count and it is well understood in the art that program/erase counts (EW_count) are a primary indicator of a memories product stage (i.e.: from beginning of life as the first product stage as described in the instant application), all the entries with low EW_counts and low fail bit counts would necessarily be an entry according to the first product stage).
Regarding claim 11, Darragh and Leem combined disclose the limitations of claim 10.
As applied, Leem further discloses wherein obtaining the plurality of corresponding destination entries based on the product stages for the plurality of memory cells comprises, if the read failure count is greater than the first value, determining that the corresponding memory cells are in a second product stage, and obtaining a second destination entry according to the second product stage (Fig 6A. It is noted that since the table entry is selected based on the fail bit count, the count is effectively an index into the table. Further, since Leem's read voltage table entry is based on the EW_count and it is well understood in the art that program/erase counts (EW_count) are a primary indicator of a memories product stage (i.e.: end of life as the second product stage as described in the instant application), all the entries with high EW_counts and high fail bit counts would necessarily be an entry according to the second product stage)
Regarding claim 14, Darragh and Leem disclose the limitations of claim 9.
As applied, Leem further discloses wherein a magnitude of the verification read voltage is between a first threshold voltage and a second threshold voltage, the first threshold voltage corresponds to the plurality of transistors at first programming times, the first programming times correspond to the first product stage, and the second threshold voltage corresponds to the plurality of transistors at second programming times, the second programming times correspond to the second product stage (Fig. 2B: 243 read voltage table. See also para. 81; "In an embodiment, the voltage register 243 may store a first read voltage table therein. The first read voltage table may be a table indicating a mapping relationship between an erase write cycle count, a reference fail bit number, and a voltage variation". It is noted that the instant application appears to indicate that the first and second threshold voltages are the lower and upper bounds of a memory lifecycle range which is analogous to the values in Leem's read voltage table. All entries in the table would necessarily be within (between) the bounding range).
Regarding claim 15, Darragh and Leem disclose the limitations of claim 11.
As applied, Darragh further discloses wherein the plurality of transistors are program selection transistors or dummy memory transistors (Fig. 15: SGD, SGS. It is noted that the instant application defines program selection transistors as TSG or BSG of Fig. 2 which are well understood in the art to be analogous to Darragh's SGD and SGS array transistors).
Regarding independent claim 16, Darragh discloses a memory comprising:
a register storing a plurality of entries (para. 60; "The data retention results or memory wear results from the cell voltage distribution changes may be tracked and stored (e.g. in the flash memory or within the controller). For example, a system table may track the changes in the cell voltage distributions and resultant changes in data retention and/or wear." It is well understood in the art that Darragh's system table would necessarily be instantiated as a bank of registers);
a plurality of transistors (Fig. 15);
a plurality of memory cells corresponding to the plurality of transistors (Fig. 15);
a drive circuit configured to output a verification read voltage to the plurality of transistors, the verification read voltage to turn on and read the plurality of transistors (Fig. 15. See also para. 82; "when respectively sensing or programming the page of cells, a sensing voltage or a programming voltage is respectively applied to a common word line (e.g. WL2)". It is well understood in the art that a sensing voltage applied to the word line is analogous to a read voltage and the application of the sensing voltage would necessarily require a circuit to generate that voltage);
a program verification circuit configured to output a plurality of indication signals to a control circuit, the plurality of indication signals to indicate a read failure count corresponding to the plurality of transistors (Fig. 4: 404 NAND trade-off engine. See also para 53; "The NAND trade-off engine 404 may dynamically measure device performance and allow for adjustments to the device based on the measurements". See also para. 151; "The proposed failed bit count (“FBC”) or error rate method may be based on the error rate measurement, approximated by taking multiple reads and measuring the FBC and by using the optimal read thresholds." It is noted that Darragh's FBC is the same metric as defined in the instant application as read failure count (Spec. para. 31)),
values of the read failure count corresponding to different product stages of the plurality of memory cells (Fig. 16 where it illustrates the increasing "FailedBitCount" between a block at 0 cycles and a block at 2k cycles. See also para. 3; "This application relates generally to memory devices. More specifically, this application relates to the measurement of wear endurance', 'Those measurements may be used for', 'end of life prediction, or adjustments to memory parameters'. It is noted that beginning of life and end of life are the indicated product stages in the instant application (Spec. para. 43)),
and the different product stages are associated with data processing times of the plurality of memory cells (Fig. 16, where it illustrates the increase of FBC due to wear. As noted above, product stage is a function of FBC, and wear is analogous to the data processing times of the instant application (Spec. para. 3));
and the control circuit configured to:
select a first destination entry from a plurality of destination entries in the register based on a product stage of a memory cell corresponding to the first destination entry (Fig. 4: 404 NAND trade-off engine. See also para 53; "The NAND trade-off engine 404 may dynamically measure device performance and allow for adjustments to the device based on the measurements", "For example, trim parameters may be adjusted based on the wear"),
the plurality of destination entries to record processing parameters for data processing of the plurality of memory cells (The instant application appears to indicate the "destination entry" is part of Register 2 which is coupled to Control circuit 1 (both of Figure 1), which is tasked with the FBC control, and which appear to be analogous to Darragh's NAND trade-off engine of above),
and the processing parameters comprising an offset voltage value and a program start voltage value for each destination entry (para. 125; " A trim parameter may include one or more parameters related to read operations, including a program rate, a program voltage level, a step-up voltage"),
wherein the offset voltage value is determined based on a threshold voltage of the memory cell corresponding to the destination entry (Darragh's use of trim parameters to adjust the program voltage level necessarily imply the modification from a known start value which must be retrieved from where it is stored (i.e.: destination entry) as also evinced from para. 96; "The initial measurement could be at manufacture and/or after the first programming and results in the reference cell voltage distribution that is used for comparing with subsequent measurements for quantifying the changes in distribution.");
and programming the plurality of memory cells based on a plurality of program voltages generated from the program start voltage value and the offset voltage value (Fig. 3. See also para 52; "In operation", "during a write operation", The FIM controller 308 may determine how the received data is to be written onto the flash memory 116 optimally. And para. 51; "The FIM controller 308 may include the algorithms implementing the independent analysis of wear"),
wherein programming the plurality of memory cells is performed according to the different product stages of the memory (para. 3; "this application relates to the measurement of wear endurance", "Those measurements may be used for", "end of life prediction, or adjustments to memory parameters". It is noted that beginning of life and end of life are the indicated product stages in the instant application (Spec. para. 43)).
While Darragh discloses verification read voltages, it is silent with respect to the specific metrics of product stages (beginning/end of life).
However, Leem teaches wherein the verification read voltage is obtained from a voltage set, the voltage set including a plurality of threshold voltages corresponding to the plurality of transistors at a plurality of different programming times (Fig. 2B Voltage Register 243. See also para. 83; "the voltage register 243 may store a third read voltage table therein. The third read voltage table may be a table indicating a mapping relationship between an erase write cycle count, a reference voltage variation, and a third voltage variation"),
wherein the threshold voltages correspond to a range of voltages of the plurality of transistors at a first product stage and a second product stage (para. 84; " a difference between third voltage variations mapped to the fifth field value indicating a first erase write cycle count among the fifth field values may be greater than a difference between third voltage variations mapped to a fifth field value indicating a second erase write cycle count greater than the first erase write cycle count". It is noted that Leem's first and second erase cycle count are analogous to the first and second product stages of the instant application),
and the verification read voltage is a threshold voltage between the first product stage and the second product stage selected based on a distribution of the threshold voltages in the first product stage and the second product stage (As noted above, Leem's second erase write cycle count is greater than the first erase write cycle count which necessarily indicates the values are between the first and second product stages);
Darragh and Leem are from the same field of endeavor as applicant’s invention directed to tracking program and read threshold voltages as a function of wear. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Darrah’s trade-off engine with Leem’s verification read voltages based on program/erase cycle correlation to reduce the number of program verify loops. Doing so would improve memory performance.
Regarding claim 17, Darragh and Leem combined disclose the limitations of claim 16.
As applied, Leem further discloses wherein the control circuit is further configured to, if the read failure count is less than or equal to a first value, select the first destination entry from the plurality of destination entries, the first destination entry corresponding to the first product stage of the plurality of memory cells (Fig. 2B: 243 read voltage table. See also para. 81; "In an embodiment, the voltage register 243 may store a first read voltage table therein. The first read voltage table may be a table indicating a mapping relationship between an erase write cycle count, a reference fail bit number, and a voltage variation". It is noted that the instant application appears to indicate that the first and second threshold voltages are the lower and upper bounds of a memory lifecycle range which is analogous to the values in Leem's read voltage table. All entries in the table would necessarily be within (between) the bounding range including the first product stage).
Regarding claim 18, Darragh and Leem combined disclose the limitations of claim 17.
As applied, Leem further discloses wherein the control circuit is further configured to, if the read failure count is greater than the first value, select a second destination entry from the plurality of destination entries, the second destination entry corresponding to the second product stage of the plurality of memory cells (Fig. 2B: 243 read voltage table. See also para. 81; "In an embodiment, the voltage register 243 may store a first read voltage table therein. The first read voltage table may be a table indicating a mapping relationship between an erase write cycle count, a reference fail bit number, and a voltage variation". It is noted that the instant application appears to indicate that the first and second threshold voltages are the lower and upper bounds of a memory lifecycle range which is analogous to the values in Leem's read voltage table. All entries in the table would necessarily be within (between) the bounding range including the second product stage).
Regarding claim 19, Darragh and Leem combined disclose the limitations of claim 17.
As applied, Darragh further discloses wherein the offset voltage value comprises at least one of a program offset voltage value or a read offset voltage value, the processing parameters further comprise at least one of the program start voltage value or a verify start voltage value, and wherein the control circuit is further configured to control the drive circuit to output at least one of the plurality of program voltages or a plurality of verification read voltages (Fig. 15. See also para. 82; "when respectively sensing or programming the page of cells, a sensing voltage or a programming voltage is respectively applied to a common word line (e.g. WL2)". It is well understood in the art that a sensing voltage applied to the word line is analogous to a read voltage and the application of the sensing voltage would necessarily require a circuit to generate that voltage).
Regarding claim 21, Darragh and Leem combined disclose the limitations of claim 18.
As applied, Darragh further discloses the plurality of transistors are program selection transistors or dummy memory transistors (Fig. 15 where it illustrates program select transistors SGD and SGS for example).
Regarding claim 22, Darragh and Leem combined disclose the limitations of claim 16.
As applied, Leem further discloses wherein a magnitude of the verification read voltage is between a first threshold voltage and a second threshold voltage, the first threshold voltage corresponds to the plurality of transistors at first programming times (para. 84. It is noted that Leem's second erase write cycle count is greater than the first erase write cycle count which necessarily indicates the values are between the first and second product stages),
the first programming times correspond to the first product stage, and the second threshold voltage corresponds to the plurality of transistors at second programming times, the second programming times correspond to the second product stage (para. 84; " a difference between third voltage variations mapped to the fifth field value indicating a first erase write cycle count among the fifth field values may be greater than a difference between third voltage variations mapped to a fifth field value indicating a second erase write cycle count greater than the first erase write cycle count". It is noted that Leem's first and second erase cycle count are analogous to the first and second product stages of the instant application).
Regarding claim 23, Darragh and Leem combined disclose the limitations of claim 22.
As applied, Leem further discloses wherein the first programming times are one-tenth of the second programming times (Fig. 6A where it illustrates example contents of a read voltage table with a column of EW cycles at 100 and a second column at 1000).
Claims 8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Darragh et al. (US 20170221573; “Darragh” – of Record) in view Leem (US 20230120696 – of Record), and further in view of Ito (US 20230207014 – of Record).
Regarding claim 8, Darragh and Leem combined disclose the limitations of claim 1.
As applied, Darragh further discloses wherein the offset voltage value comprises at least one of a program offset voltage value or a read offset voltage value (para. 125; "A trim parameter may include one or more parameters related to read operations, including", "a step-up voltage or step size"),
the processing parameters further comprise at least one of the program start voltage value or a verify start voltage value (para. 125; "The initial setting of the trim parameters may be set up for the fastest and most aggressive programming mode possible". It is noted that an initial setting is necessarily a "program start voltage value"),
and the control method further comprises:
outputting at least one of the plurality of program voltages and a plurality of verification read voltages (Fig. 15. See also para. 82; "when respectively sensing or programming the page of cells, a sensing voltage or a programming voltage is respectively applied to a common word line (e.g. WL2)");
Darragh and Leem combined are silent with respect to the specific boundary range voltage levels.
However, Ito teaches setting a lowest voltage value of the plurality of program voltages as the program start voltage value (Fig. 11 where it illustrates an MLC NAND flash standard write/verify sequence which starts at the lowest value (VPGM1). See also para. 104; "the program voltage VPGM applied to the selected word line WL is sequentially increased for each loop". It is noted that if each loop is increased, it necessarily starts at the lowest voltage value);
and controlling a lowest voltage value of the plurality of verification read voltages to be the verify start voltage value for the plurality of verification read voltages with the read offset voltage value as a step unit (Fig. 11 where it illustrates the verify sequence which starts at the lowest value (VrA) with step increments in subsequent loops up to VrG as needed).
Darragh and Leem combined, along with Ito are from the same field of endeavor as applicant’s invention directed to determining specific program and read threshold voltages for a memory array. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Darrah’s trim parameters with Leem’s verification read voltages based on program/erase cycle correlation and with Ito’s initial program and verification voltages to reduce the number of program verify loops. Doing so would increase memory speed and reduce wear over time.
Regarding claim 20, Darragh and Leem combined disclose the limitations of claim 17.
As applied, Darragh further discloses the offset voltage value comprises at least one of a program offset voltage value or a read offset voltage value (para. 125; "A trim parameter may include one or more parameters related to read operations, including", "a program voltage level", "a step-up voltage". It is noted that the instant application refers to various offset voltages and merely indicates that they are a "step unit" (Spec. para. 68) and therefore, analogous to Darragh's step-up voltage parameter. Additionally, the instant application appears to indicate the "destination entry" is part of Register 2 which is coupled to Control circuit 1 (both of Figure 1), which is tasked with the FBC control, and which appear to be analogous to Darragh's NAND trade-off engine of above),
Darragh and Leem are silent with respect to the specific boundary range voltage levels.
However, Ito teaches the processing parameters further comprise at least one of the program start voltage value or a verify start voltage value (Fig. 11 where it illustrates a MLC NAND flash standard write/verify sequence which starts at the lowest value (VPGM1),
and the control circuit is further configured to:
set a lowest voltage value of the plurality of program voltages as the program start voltage value (Fig. 13 where it illustrates the row decoder 25 which sets the program voltage on the word line. See also para. 104; "the program voltage VPGM applied to the selected word line WL is sequentially increased for each loop". It is noted that if each loop is increased, it necessarily starts at the lowest voltage value);
and control a lowest voltage value of a plurality of verification read voltages to be the verify start voltage value for the plurality of verification read voltages with the read offset voltage value as a step unit (Fig. 11 where it illustrates the verify sequence which starts at the lowest value (VrA) with step increments in subsequent loops up to VrG as needed).
Darragh and Leem combined, along with Ito are from the same field of endeavor as applicant’s invention directed to determining specific program and read threshold voltages for a memory array. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Darrah’s trim parameters with Leem’s verification read voltages based on program/erase cycle correlation and with Ito’s initial program and verification voltages to reduce the number of program verify loops. Doing so would increase memory speed and reduce wear over time.
Response to Arguments
Applicant's arguments filed January 26, 2026, have been fully considered but they are not persuasive. Applicant contends on pg. 10 of Remarks that the anticipation rejection of claim 1 is improper because Darragh fails to disclose the feature of a verification read voltage is a threshold voltage between a first product stage and a second product stage selected based on a distribution of threshold voltages in the first product stage and the second product.
Different facts from the references are applied to the amendments of the claim rendering the argument moot because of the new ground of rejection based on the references cited above, as well as the newly cited portions of the references previously presented.
For at least these reasons, the rejection of claim 1 is deemed proper and maintained.
Independent claims 9 and 16, being similarly amended, are also deemed proper and maintained for the same reasons.
Conclusion
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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