DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su et al, US Patent Application Publication 2017/0133351 (as cited in previous Office Action)
Regarding claim 1, Su teaches semiconductor package comprising:
a base die 302/86/84 having a first surface and a second surface opposite each other;
a first group of core dies 434 stacked on the first surface of the base die and electrically connected to the base die (via wirebonds coming from the sides of 434);
a mount member 66 facing the second surface of the base die;
a second group of core dies 534 between the base die and the mount member, the second group of core dies being stacked on the second surface of the base die and electrically connected to the base die; and
an interface 32 for an electrical connection between the base die and the mount member (figure 16)
Regarding claim 2, Su teaches an area of the base die is larger an area of the first group of the core dies and larger than an area of the second group of the core dies (figure 16).
Regarding claim 3, Su teaches the first surface of the base die and the second surface of the base die each include a mounting area and a peripheral area extending in at least one direction outward from the mounting area, the first group of the core dies are stacked on the mounting area of the first surface of the base die, the second group of the core dies are stacked on mounting area of the second surface of the base die, and the interface provides an electric connection between the peripheral area of the first surface or the second surface of the base die and the mount member (figure 16, wherein the peripheral areas are the area outside of the mount areas).
Regarding claim 4, Su teaches the interface 32 includes at least one of a copper pillar and a wire [0016].
Regarding claims 5-8, Su teaches the interface includes the copper pillar, and the copper pillar provides an electric connection between the peripheral area of the second surface of the base die and the mount member, the interface includes the wire, and the wire provides an electrical connection between the peripheral area of the first surface of the base die and the mount member, wherein the interface includes the copper pillar and the wire, the copper pillar provides an electrical connection between the peripheral area of the second surface of the base die and the mount member, and the wire provides an electrical connection between the peripheral area of the first surface of the base die and the mount member, the copper pillar is configured to provide a signal transmission path, and the wire is configured to provide a power supply path (Note: the through silicon via 32 is the same in terms of patentability to a pillar and a wire, which as configured to provide both a signal transmission path and a power path since they are made of copper).
Regarding claim 9, Su teaches a processing chip, wherein the mount member 66 is an interposer, the processing chip is on the interposer, and the interface provides an electrical connection for signal transmission between the processing chip and first group of the core dies and signal transmission between the processing chip and the second group of the core dies (figure 16 and [0028]).
Regarding claim 10, Su teaches the mount member (66 with 58) is a processing chip, and the interface provides an electrical connection for signal transmission between the processing chip and the first group of the core dies and signal transmission between the processing chip and the second group of the core dies (figure 16 and [0028]).
Regarding claim 12, Su teaches a number of the first group of the core dies is different than a number of the second group of the core dies (figure 16).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su et al, US Patent Application Publication 2017/0133351 (as cited in previous Office Action).
Regarding claims 11 and 13, Su fails to teach a group of the core dies equals a number of the second group of the core dies and the number of the first group of the core dies is greater than the number of the second group of the core dies.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim(s) 14-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su et al, US Patent Application Publication 2017/0133351 in view of Lee et al, US Patent Application Publication 2008/0105984 (both as cited in previous Office Action).
Regarding claim 14, Su teaches a high-bandwidth memory semiconductor package comprising:
a base die 302/86/84 having a first surface and a second surface opposite each other;
a first group of core dies 434 stacked on the first surface of the base die and electrically connected to the base die through (via wirebonds coming from the sides of 434);
a mount member 66/56/58 facing the second surface of the base die;
a second group of core dies 534 between the base die and the mount member, the second group of core dies stacked on the second surface of the base die and electrically connected to the base die through a second through-silicon via (72, 538, which are electrically connected to 302 via interconnects, 32, and 84); and
an interface 32 for an electrical connection between the base die and the mount member, wherein
the base die includes a redistribution layer (RDL) 302, a physical layer (PHY) interface 86, and a direct access (DA) interface 84,
an area of the base die is larger than an area of the first group of the core dies and larger than an area of the second group of the core dies,
the first surface of the base die and the second surface of the base die each include a mounting area and a peripheral area (wherein the peripheral areas are the area outside of the mount areas) extending in at least one direction outward of the mounting area,
the first group of the core dies are stacked on the mounting area of the first surface of the base die, the second group of the core dies are stacked on the mounting area of the second surface of the base die, and the PHY interface and the DA interface are in a peripheral region of the base die and electrically connected to the mount member through the interface (figure 16).
Su fails to teach electrically connected to the base die to the first core of dies through a first through-silicon via.
However, Lee teaches an alternative, yet conventionally-used stacked die packaging structure, which uses flip chip bonding to electrically connect the stack dies to the base die. Figure 12 of Lee shows electrically connected to the base die (either 490 or 410) to the first core of dies (either 405 or 406) through a first through-silicon via (shown as 421, 431, 441, and 451)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee with that of Su because flip chip bonding is an alternative, yet conventionally-used stacked die packaging structure, which uses flip chip bonding to electrically connect the stack dies to the base die.
Regarding claim 15, Su teaches the base die further includes a processing circuit (RDL structure, figure 16).
Regarding claim 16, Su teaches the interface includes at least one of a copper pillar between the peripheral area of the second surface of the base die and the mount member, or a wire between the peripheral area of the first surface of the base die and the mount member (figure 16).
Regarding claim 17, Lee teaches a number of the second group of the core dies is less than or equal to a number of the first group of the core dies (figure 12).
Regarding claim 18, Lee and Su fail to teach a thickness of the base die is 50 mm to 130 mm.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Allowable Subject Matter
Claims19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent 9,851,401, issued to Kim et al, discloses a stacked memory device and semiconductor memory system. US Patent 11,416,425, issued to Kim, discloses a memory device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale E Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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QVJ
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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