DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Examiner acknowledges the amending of claims 1, 8, 18. Claims 9, 11-17 remain withdrawn, as each one continues to read on a previously non-elected embodiment.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8, 18 (gate identification number not disposed between two sides of line arrangement area) have been considered but are moot because the new ground of rejection does not rely on any reference interpretation applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. New interpretation of Kwon used to reject amended claims (Remarks pgs. 9-12).
Applicant argues Kwon in view of Zhao does not disclose “each of… the power lines being disposed in the display area; … wherein the line arrangement area and a gate driving unit, which is connected to the gate lines extending in a first direction, are disposed in the non-display area” (Remarks pgs. 12-13).
Examiner disagrees. Gate driving unit present in both display area and non-display area
(annotated fig. G). One gate driving chip/drive unit present in display area (top 400 in annotated fig. G),
and one present in non-display area (bottom 400). Line arrangement area LAA also overlaps with area outside of display area DA (i.e. the non-display area) (annotated fig. 1 + annotated fig. G). Power/signal lines in annotated fig. 1a also present in both display area DA and in non-display area outside of DA. Note, Examiner interprets “each of the gate lines, the data lines and the power lines” to mean at least one of the gate lines, at least one of the data lines, and at least one of the power lines are present within the display area (i.e. “each of” the 3-element list containing gate lines, data lines, and power lines), NOT interpreted to mean all of the gate lines, all of the data lines, and all of the power lines are present within the display area.
All non-withdrawn claims remain rejected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1, 8, 18 (and 2-7, 10 via dependency) rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 8, 18 indefinite due to “a gate driving unit” in line 13, line 14, line 16, respectively. A “gate drive unit” is already introduced in the claims prior to “a gate driving unit”. It is unclear whether the gate driving unit is a new and different element, or if the gate driving unit is equivalent to the gate drive unit. Examiner interprets the terminology + elements to be equivalent. Applicant is advised to keep terminology consistent and remove redundant references to/introductions of a “gate drive unit”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
First/Second Lines now include only the lines present within annotated fig. Q region LR.
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Claim(s) 1-5, 8, 10, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US-8354672-B2) in view of Zhao (CN-111128965-A, Zhao_English used as translation herewith).
Regarding claim 1, Kwon discloses a display device (fig. 1) comprising: gate lines (fig. 1 horizontal portion of 121 within 10, col. 3 lines 51-52), data lines (fig. 1 vertical portion of 171 within 10, col. 3 lines 51-52), and power lines electrically connected to sub-pixels (annotated fig. 1a lines within Power Line region connected electrically to sub-pixels P, col. 3 lines 52-66, col 4 lines 4-10) in a display area of a display panel (annotated fig. G display area DA, see italics below), each of the gate lines, the data lines and the power lines being disposed in the display area (annotated fig. G 121,171,annotated fig. 1a Power Line region lines all in display area DA); fan-out lines in a non-display area (annotated fig. G non-display area (non-DA) is interpreted to be the area outside of both DA and 10) of the display panel and electrically connected to the data lines (annotated fig. G angled portion of 171 within non-DA electrically connected to vertical portion of 171 within DA, col 3 lines 58-60); gate control lines electrically connected to a gate drive unit disposed in the non-display area (annotated fig. G angled portion of 121 + (fig. 2 129 + 195, col. 4 line 65 - col. 5 line 10) within non-DA electrically connected to bottom 400, col 3 lines 58-62, note fig. G shows incomplete design/device, 121 lines will continue down to bottom + bottom half of angled 121+fig. 2 129 + 195 will reside within non-DA); and line number identification patterns in a line arrangement area (LAA) through which one or more lines of the gate lines, the data lines, the fan-out lines, the gate control lines, and the power lines extend (annotated fig. 1 angled 171 and 121 + (fig. 2 129 + 195) extend through LAA, fig. 2 125 near 129 within LAA, col 4 lines 25-27), the line number identification patterns being in a floating state (fig. 3 125 electrically isolated, col 4 lines 44-51 + 56-60), wherein the line arrangement area and a gate driving unit, which is connected to the gate lines extending in a first direction, are disposed in the non-display area (annotated figs. 1 + G Line Arrangement Area and gate driving unit (bottom 400) connected to gate lines (angled portion of 121) + 129 + 195 extending in first direction (left to right in fig. 1), and disposed in non-display area (outside of annotated fig. G DA)), wherein the one or more lines includes first lines (annotated fig. 2 First Lines only those within annotated fig. Q LR), each of which is disposed between the line number identification patterns (annotated fig. 2 First Lines disposed between 125), and second lines (annotated fig. 2 Second Lines only those within annotated fig. Q LR), each of which overlaps a portion of each of the line number identification patterns in a thickness direction of the display device perpendicular to a substrate (annotated figs. 1b + 2 + 3 each Second Line (121 + 129 + 195) overlaps 125 in thickness direction D perpendicular to substrate 100, col. 4 lines 10-15) wherein the first lines and the line number identification patterns are disposed on a same layer and include a same material (fig. 3 129 + 125 within fig. 1 LAA same material and layer, fig. 3 shows Second Line 129, but First Line 129 on same layer 100, col. 4 lines 11-14 + 25-36), and the second lines are disposed on a different layer than the line number identification patterns in the thickness direction perpendicular to the substrate (fig. 3 Second Lines (195 component) different layer than 125 in thickness direction), wherein each of the first lines extends from a first side of the line arrangement area to a second side of the line arrangement area (annotated fig. Q first lines within line region LR extend from first side FS to second side SS of LAA), which is an opposite side to the first side in a second direction different from the first direction (SS opposite FS in Second Direction different from left to right first direction), and the line number identification patterns are disposed between the first side and the second side of the line arrangement area in the second direction (line number identification patterns within IDR between FS and SS of LAA in Second Direction (i.e. within region B)).
Kwon does not disclose the second lines are disposed on a different layer than the first lines.
Zhao discloses an array substrate and display panel with lines on a first patterned layer and lines on a second patterned layer separated in a thickness direction (fig. 3 11 on first patterned layer, 32 on second patterned layer, lines 164-170).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device in Kwon by placing second lines on different layer than the first lines in the thickness direction perpendicular to the substrate.
One of ordinary skill in the art would have been motivated to make this modification as including another layer would provide more space to include lines in a thickness direction of the display substrate. Also, increasing the thickness of the substrate with multiple layers would improve the durability.
Examiner interprets “gate control lines” to be the combination of the angled portion of 121 in fig. 1 and 129 + 195 in fig. 2.
Examiner interprets “display area” to be any region of the device that contains an array of pixels displaying images, as suggested by Applicant (Specification 0005 lines 1-3). For clarity, Examiner notes display area can also contain portions that DO NOT have pixels, as long as somewhere within the display area there is a pixel array displaying images.
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Regarding claim 2, Kwon, as modified by Zhao, discloses the display device of claim 1, wherein the line number identification patterns are disposed side by side at a preset interval in the line arrangement area (fig. 2 125), the first lines of the one or more lines do not overlap the line number identification patterns (annotated fig. 2 First Lines are between + do not overlap 125 in orientation indicated by dashed line), and at least one insulating layer is interposed between the line number identification patterns and the second lines (annotated fig. 2 + 3 insulating layer 180 between 125 and Second Lines 195 col. 4 lines 60-65).
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Regarding claim 3, Kwon, as modified by Zhao, discloses the display device of claim 2, wherein the line number identification patterns and the first lines contain are portions of a first patterned layer in the display panel (fig. 3 125 + 129 in fig. 1 LAA same material and layer), the line number identification patterns are adjacent to the first lines or in areas between the first lines and are not electrically connected to the first lines (annotated fig. 2 125 adjacent to First Lines + in area between First Lines, fig. 3 125 electrically isolated, col 4 lines 44-51 + 56-60), the second lines are portions of a second patterned layer of the display panel (see modification claim 1 rejection) and overlap the line number identification patterns with the at least one insulating layer interposed between the second lines and the line number identification patterns (annotated fig. 2 + 3 insulating layer 180 between 125 and Second Lines 195, 195 overlap 125, col. 4 lines 60-65)
Regarding claim 4, Kwon, as modified by Zhao, discloses the display device of claim 3, wherein at least one of a size of the line number identification patterns and a formation width of the line number identification patterns is smaller than a sum of a distance between two lines adjacent to each other among the one or more lines and widths of the two lines (annotated fig. 2b FW < DLW).
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Regarding claim 5, Kwon, as modified by Zhao, discloses the display device of claim 2, wherein the one or more lines includes odd-numbered lines and even-numbered lines, the first lines are the odd-numbered lines and are formed and disposed in the line arrangement area with the same material as the line number identification patterns through a same patterning process (fig. 3 125 + 129 in fig. 1 LAA same material and layer, fig. 3 shows Second Line 129, but First Line 129 is on same layer, col. 4 lines 25-36), the line number identification patterns are respectively adjacent to the odd-numbered lines (annotated fig. 2 125 adjacent to odd-numbered lines/First Lines), and the second lines are the even-numbered lines and respectively overlap the line number identification patterns with the at least one insulating layer interposed between the second lines and the line number identification patterns (annotated fig. 2 + 3 insulating layer 180 between 125 and Second Lines 195, 195 overlap 125, col. 4 lines 60-65)
def. adjacent – not distant (Merriam-Webster def. 1a)
For claims 8 + 10 only, first lines are lines corresponding to pads with identification patterns (annotated fig. 2 Second Lines only those within annotated fig. Q LR). Second lines are lines corresponding to pads without identification patterns (annotated fig. 2 First Lines only those within annotated fig. Q LR). Lines are swapped.
Regarding claim 8, Kwon discloses a display device (fig. 1) comprising: gate lines (fig. 1 horizontal portion of 121 within 10, col. 3 lines 51-52), data lines (fig. 1 vertical portion of 171 within 10, col. 3 lines 51-52), and power lines electrically connected to sub-pixels (annotated fig. 1a lines within Power Line region connected electrically to sub-pixels P, col. 3 lines 52-66, col 4 lines 4-10) formed in a display area of a display panel (annotated fig. G display area DA), each of the gate lines, the data lines and the power lines being disposed in the display area (annotated fig. G 121,171,annotated fig. 1a Power Line region lines all in display area DA); fan-out lines formed in a non-display area (annotated fig. G non-display area (non-DA) is interpreted to be the area outside of both DA and 10) of the display panel and electrically connected to the data lines (fig. 1 angled portion of 171 within non-DA electrically connected to vertical portion of 171 within DA, col 3 lines 58-60); gate control lines electrically connected to a gate drive unit disposed in the non-display area (fig. 1 angled portion of 121 + (fig. 2 129 + 195, col. 4 line 65 – col. 5 line 10) within non-DA electrically connected to bottom 400, col 3 lines 58-62); first lines (annotated fig. 2 Second Lines only those within annotated fig. Q LR) and second lines (annotated fig. 2 First Lines only those within annotated fig. Q LR) in a line arrangement area (annotated fig. 1 angled 171 and 121 + (fig. 2 129) extend through LAA, fig. 2 125 near 129 within LAA, col 4 lines 25-27), the first lines and the second lines being selected from a group consisting of the gate lines, the data lines, the power lines, the fan-out lines, and the gate control lines (First and Second Lines are gate control lines); and line number identification patterns disposed in the line arrangement area and in a floating state electrically separated from the first lines and the second lines (fig. 3 125 electrically isolated, col 4 lines 44-51 + 56-60, 125 in LAA), wherein the line arrangement area and a gate driving unit, which is connected to the gate lines extending in a first direction, are disposed in the non-display area (annotated figs. 1 + G Line Arrangement Area and gate driving unit (bottom 400) connected to gate lines (angled portion of 121) + 129 + 195 extending in first direction (left to right in fig. 1), and disposed in non-display area (outside of annotated fig. G DA)), wherein each of the first lines is disposed between the line number identification patterns (annotated fig. 2 Second Lines disposed between 125), and each of the second lines overlaps a portion of each of the line number identification patterns in a thickness direction of the display device perpendicular to a substrate (annotated figs. 1b + 2 + 3 each First Line (121 + 129 + 195) overlaps 125 in thickness direction D perpendicular to substrate 100, col. 4 lines 10-15), and wherein the first lines and the line number identification patterns are disposed on a same layer and include a same material (fig. 3 129 + 125 within fig. 1 LAA same material and layer, fig. 3 shows First Line 129, but Second Line 129 on same layer 100, col. 4 lines 11-14 + 25-36), and the second lines are disposed on a different layer than the line number identification patterns in the thickness direction perpendicular to the substrate (fig. 3 First Lines (195 component) different layer than 125 in thickness direction), wherein each of the first lines extends from a first side of the line arrangement area to a second side of the line arrangement area (annotated fig. Q first lines within line region LR extend from first side FS to second side SS of LAA), which is an opposite side to the first side in a second direction different from the first direction (SS opposite FS in Second Direction different from left to right first direction), and the line number identification patterns are disposed between the first side and the second side of the line arrangement area in the second direction (line number identification patterns within IDR between FS and SS of LAA in Second Direction).
Kwon does not disclose the second lines are disposed on a different layer than the first lines.
Zhao discloses an array substrate and display panel with lines on a first patterned layer and lines on a second patterned layer (fig. 3 11 on first patterned layer, 32 on second patterned layer, lines 164-170).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device in Kwon by placing second lines on different layer than the first lines in the thickness direction perpendicular to the substrate.
One of ordinary skill in the art would have been motivated to make this modification as including a second layer would provide more space to include lines in a thickness direction of the display substrate. Also, increasing the thickness of the substrate with multiple layers would improve the durability.
Examiner interprets “gate control lines” to be the combination of the angled portion of 121 in fig. 1 and 129 in fig. 2.
Examiner interprets “display area” to be any region of the device that contains an array of pixels displaying images, as suggested by Applicant (Specification 0005 lines 1-3). For clarity, Examiner notes display area can also contain portions that DO NOT have pixels, as long as somewhere within the display area there is a pixel array displaying images.
Regarding claim 10, Kwon, as modified by Zhao, discloses the display device of claim 8, wherein the first lines are formed simultaneously with the line number identification patterns through a same patterning process that forms the line number identification patterns (fig. 3 125 + 129 in fig. 1 LAA same material and layer, fig. 3 shows First Line 129, col. 4 lines 25-36), and at least one insulating layer is interposed between the line number identification patterns and the second lines (annotated fig. 2 + 3 insulating layer 180 between 125 and First Lines 195 col. 4 lines 60-65).
First Lines and Second Lines are swapped for claims 8+10.
Regarding claim 18, Kwan discloses an electronic device comprising: a display device (fig. 1); and a main processor controlling an operation of the display device (fig. 1 main processor “external printed circuit boards” not shown control operation of the display device, col. 3 line 60 – col. 4 line 5), wherein the display device comprises: gate lines (fig. 1 horizontal portion of 121 within 10, col. 3 lines 51-52), data lines (fig. 1 vertical portion of 171 within 10, col. 3 lines 51-52), and power lines electrically connected to sub-pixels (annotated fig. 1a lines within Power Line region connected electrically to sub-pixels P, col. 3 lines 52-66, col 4 lines 4-10) in a display area of a display panel (annotated fig. G display area DA, see italics below), each of the gate lines, the data lines and the power lines being disposed in the display area (annotated fig. G 121,171,annotated fig. 1a Power Line region lines all in display area DA); fan-out lines in a non-display area (annotated fig. G non-display area (non-DA) is interpreted to be the area outside of both DA and 10) of the display panel and electrically connected to the data lines (annotated fig. G angled portion of 171 within non-DA electrically connected to vertical portion of 171 within DA, col 3 lines 58-60); gate control lines electrically connected to a gate drive unit disposed in the non-display area (annotated fig. G angled portion of 121 + (fig. 2 129 + 195, col. 4 line 65 - col. 5 line 10) within non-DA electrically connected to bottom 400, col 3 lines 58-62, note fig. G shows incomplete design/device, 121 lines will continue down to bottom + bottom half of angled 121+fig. 2 129 + 195 will reside within non-DA); and line number identification patterns in a line arrangement area (LAA) through which one or more lines of the gate lines, the data lines, the fan-out lines, the gate control lines, and the power lines extend (annotated fig. 1 angled 171 and 121 + (fig. 2 129 + 195) extend through LAA, fig. 2 125 near 129 within LAA, col 4 lines 25-27), the line number identification patterns being in a floating state (fig. 3 125 electrically isolated, col 4 lines 44-51 + 56-60), wherein the line arrangement area and a gate driving unit, which is connected to the gate lines extending in a first direction, are disposed in the non-display area (annotated figs. 1 + G Line Arrangement Area and gate driving unit (bottom 400) connected to gate lines (angled portion of 121) + 129 + 195 extending in first direction (left to right in fig. 1), and disposed in non-display area (outside of annotated fig. G DA)), wherein the one or more lines includes first lines (annotated fig. 2 First Lines only those within annotated fig. Q LR), each of which is disposed between the line number identification patterns (annotated fig. 2 First Lines disposed between 125), and second lines (annotated fig. 2 Second Lines only those within annotated fig. Q LR), each of which overlaps a portion of each of the line number identification patterns in a thickness direction of the display device perpendicular to a substrate (annotated figs. 1b + 2 + 3 each Second Line (121 + 129 + 195) overlaps 125 in thickness direction D perpendicular to substrate 100, col. 4 lines 10-15) wherein the first lines and the line number identification patterns are disposed on a same layer and include a same material (fig. 3 129 + 125 within fig. 1 LAA same material and layer, fig. 3 shows Second Line 129, but First Line 129 on same layer 100, col. 4 lines 11-14 + 25-36), and the second lines are disposed on a different layer than the line number identification patterns in the thickness direction perpendicular to the substrate (fig. 3 Second Lines (195 component) different layer than 125 in thickness direction), wherein each of the first lines extends from a first side of the line arrangement area to a second side of the line arrangement area (annotated fig. Q first lines within line region LR extend from first side FS to second side SS of LAA), which is an opposite side to the first side in a second direction different from the first direction (SS opposite FS in Second Direction different from left to right first direction), and the line number identification patterns are disposed between the first side and the second side of the line arrangement area in the second direction (line number identification patterns within IDR between FS and SS of LAA in Second Direction).
Kwon does not disclose the second lines are disposed on a different layer than the first lines.
Zhao discloses an array substrate and display panel with lines on a first patterned layer and lines on a second patterned layer separated in a thickness direction (fig. 3 11 on first patterned layer, 32 on second patterned layer, lines 164-170).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device in Kwon by placing second lines on different layer than the first lines in the thickness direction perpendicular to the substrate.
One of ordinary skill in the art would have been motivated to make this modification as including another layer would provide more space to include lines in a thickness direction of the display substrate. Also, increasing the thickness of the substrate with multiple layers would improve the durability.
Examiner interprets “gate control lines” to be the combination of the angled portion of 121 in fig. 1 and 129 + 195 in fig. 2.
Examiner interprets “display area” to be any region of the device that contains an array of pixels displaying images, as suggested by Applicant (Specification 0005 lines 1-3). For clarity, Examiner notes display area can also contain portions that DO NOT have pixels, as long as somewhere within the display area there is a pixel array displaying images.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Zhao and Lee et al. (EP-3916710-A1).
Regarding claim 6, Kwon, as modified by Zhao, discloses the display device of claim 5, wherein the odd-numbered lines and the even-numbered lines are connected through respective contact holes to the data lines or the power lines (fig. 3 129 connected to fig. 1 400 + Power Lines through hole fig. 3 181, col 4 lines 21-24).
Kwon, as modified by Zhao, does not disclose the connections being made in a one-to-one manner.
Lee discloses a display panel with lines connected in a one-to-one manner (Abstract).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have connected the odd-numbered lines and even-numbered lines to the power lines in a one-to-one manner.
One of ordinary skill in the art would have been motivated to make this modification as providing a unique power line for each odd-numbered and even-numbered line would prevent multiple odd+even lines from becoming inoperable in case of failure of a single power line. The impact would be isolated to the odd/even line that is connected to the defective power line.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Zhao and Kwak et al. (US-7528544-B2).
Regarding claim 7, Kwon, as modified by Zhao, discloses the display device of claim 2, wherein the first lines and the line number identification patterns are formed of a same material (First Lines (129 + angled 121) and 125 formed of same material, col 4 lines 25-36).
Kwon, as modified by Zhao, does not disclose wherein a gate electrode or source and drain electrodes of a thin film transistor are formed of a same material through a same patterning process as the first lines and line number identification patterns, and the second lines are simultaneously formed of a same material of an electrode selected from a group consisting of the source and drain electrodes, and a capacitor electrode, a first anode connection electrode, a second anode connection electrode, a pixel electrode, a common electrode, and any one of touch electrodes of a touch sensing unit.
Kwak discloses a display panel with lines that comprise a same material as a material of the gate electrodes of the display region (Claim 4). Kwak also discloses a display panel with lines that comprise a same material as a material of the source and/or drain electrodes of the display region (Claim 5).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have used first lines (second lines) that are formed of the same material through the same patterning process as a gate electrode (source/drain electrode).
One of ordinary skill in the art would have been motivated to make this modification as using the same material for multiple components in the same layer would save time and money during construction/assembly.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.E./Examiner, Art Unit 2828
/MINSUN O HARVEY/Supervisory Patent Examiner, Art Unit 2828