Prosecution Insights
Last updated: April 19, 2026
Application No. 18/508,445

INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102§103
Filed
Nov 14, 2023
Examiner
DOAN, THERESA T
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
93%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
791 granted / 896 resolved
+20.3% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
24 currently pending
Career history
920
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
42.2%
+2.2% vs TC avg
§102
38.4%
-1.6% vs TC avg
§112
3.3%
-36.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 896 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 6-7 and 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (2019/0221669). Regarding claim 1, Lee (Fig. 8A) discloses an integrated circuit device 300 comprising: a substrate 110 having a plurality of active regions A1 defined by a device isolation trench 112T ([0050]); a device isolation structure 112 including an etching induction film 112A and filling the device isolation trench 112T ([0084]); the etching induction film 112A covering a bottom surface of the device isolation trench 112T ([0085]); a word line trench 130R intersecting with the plurality of active regions A1 and the device isolation structure 112 and extending in a first lateral direction ([0065]); a gate dielectric film 120 covering an inner wall of the word line trench 130R ([0061]); and a word line 130 filling a portion of the word line trench 130R on the gate dielectric film 120, wherein each of the plurality of active regions A1 comprises a fin body portion FB under the word line 130 and a saddle fin portion TF protruding from the fin body portion FB toward the word line 130, and at least a portion of the etching induction film 112A is exposed by the word line trench 130R (Fig. 8A). Regarding claim 6, Lee (Fig. 8A) discloses wherein the word line trench 130R comprises a first bottom surface GTB2 at which the saddle fin portion TF is exposed and a second bottom surface GTB1 at which the device isolation structure is exposed, and a top of the first bottom surface GTB2 is at a higher level than a top of the second bottom surface GTB1 in a vertical direction. Regarding claim 7, Lee (Fig. 8A) discloses wherein the word line trench 130R comprises a first bottom surface GTB2 at which the saddle fin TF portion is exposed and a second bottom surface GTB1 at which the device isolation structure 112 is exposed, and the portion of the etching induction film 312A is exposed through the second bottom surface GTB1. Regarding claim 17, Lee (Fig. 8A) discloses an integrated circuit device comprising: a substrate 110 having a cell array region 322 ([0080]), a peripheral circuit region 324 ([0079]), and an interface region ([0075]) between the cell array region 322 and the peripheral circuit region 324; a plurality of cell active regions A1 defined by a device isolation trench 112T in the cell array region 322; a peripheral circuit active region A1 defined by an interface trench 312T in the peripheral circuit region 326; a device isolation structure 112 including an etching induction film 112A and filling the device isolation trench 112B; the etching induction film 112A covering a bottom surface 112T of the device isolation trench 112T in the cell array region 322; an interface isolation structure 312 filling the interface trench 312T in the peripheral circuit region 324; a word line trench 130 intersecting with the plurality of cell active regions A1 and the device isolation structure 112 in the cell array region 322 and extending in a first lateral direction, the word line trench 130R having a first bottom surface GTB1 exposing the plurality of cell active regions A1 and a second bottom surface GTB2 exposing the device isolation structure 112; a gate dielectric film 120 covering an inner wall of the word line trench 130R ([0061]); and a word line 130 filling a portion of the word line trench 130R on the gate dielectric film 120, wherein a portion of the etching induction film 112A is exposed through the second bottom surface GTB2 (Fig. 8A, [0055]). Regarding claim 18, Lee (Fig. 8A) discloses wherein each of the plurality of cell active regions 322 comprises a fin body portion FB under the word line 130 and a saddle fin portion TF protruding from the fin body portion FB toward the word line 130. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (2019/0221669) in view of Kim et al. (2020/0020697). Regarding claim 9, Lee (Fig. 8A) discloses the etching induction film 312 comprises silicon oxide ([0087]). Lee discloses all the claimed limitations as discussed above, except for the etching induction film comprises silicon oxide doped with fluorine (F). Kim (Fig. 11A) discloses the etching induction film 282 comprises silicon oxide doped with fluorine (F) (see [0170]) for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416. Accordingly, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the device of Lee by forming the etching induction film comprises silicon oxide doped with fluorine (F) for the intended use as a matter of design choice, as taught by Kim (see [0170]). Regarding claim 8, Lee (Fig. 8A) discloses wherein the fin body portion FB has a first height in a vertical direction, the saddle fin portion TF has a second height in the vertical direction, but does not disclose a ratio of the second height to the first height is 0.2 or higher. However, the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. In Gardner v. TEC Systems, Inc., 725 F. 2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to form a ratio of the second height to the first height is 0.2 or higher as claimed, because the dimensions can be varied for other implementations. Allowable Subject Matter Claims 2-5, 10 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art of record fails to disclose all the limitations recited in the above claims. Specifically, the prior art of record fails to disclose wherein the device isolation structure has an overlap area overlapping the word line in a vertical direction, the overlap area comprises a first region between a first active region and a second active region adjacent to the first active region in the first lateral direction, the first active region and the second active region being selected from the plurality of active regions, and a second region between the first active region and a third active region adjacent to the first active region in the first lateral direction, the first active region and the third active region being selected from the plurality of active regions, the third active region facing the second active region with the first active region therebetween in the first lateral direction, and the device isolation structure of the first region comprises the etching induction film (claim 2); or wherein the etching induction film has a first oxygen content and a first fluorine content, the first oxygen content is 66 at% or less, based on a total element content of the etching induction film, and the first fluorine content is 14 at% or less, based on the total element content of the etching induction film (claim 10); or further comprising: a deposition inhibition film covering an upper sidewall of the peripheral circuit active region (claim 19). The dependent claims being further limiting and definite are also allowable. Claims 11-16 are allowed. The following is an examiner's statement of reasons for allowance: The prior art of record neither anticipates nor renders obvious all the limitations in the base claim 11. Specifically, the combination of an integrated circuit device comprising: wherein the device isolation structure has an overlap area overlapping the word line in a vertical direction, and the overlap area comprising: a first region between a first active region and a second active region adjacent to the first active region in the first lateral direction, the first active region and the second active region being selected from the plurality of active regions, and a second region between the first active region and a third active region adjacent to the first active region in the first lateral direction, the first active region and the third active region being selected from the plurality of active regions, the third active region facing the second active region with the first active region therebetween in the first lateral direction, and wherein the etching induction film is exposed through the word line trench in the first region and covers the bottom surface and a lower inner wall of the device isolation trench in the second region. The dependent claims being further limiting and definite are also allowable. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to THERESA T DOAN whose telephone number is (571)272-1704. The examiner can normally be reached on Monday, Tuesday, Wednesday and Thursday from 7:00AM - 3:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THERESA T DOAN/ Primary Examiner, Art Unit 2814
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Prosecution Timeline

Nov 14, 2023
Application Filed
Mar 13, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
93%
With Interview (+5.1%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 896 resolved cases by this examiner. Grant probability derived from career allow rate.

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