Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/14/2023, 01/07/2025, and 02/20/2025 was filed after the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 9-12, 17-21, and 24 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al, US 20230411358 A1. .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
.
Xie teaches:
A semiconductor device (: par 52-73, figures 1-31) comprising:
a plurality of nanodevices including a plurality of upper transistors (figure
31: transistors formed by nano stacks elements 192, 194, 196) and a plurality of
lower transistors (figure 31: transistors formed by nano stacks elements
111, 112), wherein the plurality of nanodevices include an upper active region
( figure 31, one of elements 192, 194, 196) and a lower active region (:
figure 31, one of elements 111, 112) that are offset from each other across the
plurality of upper transistors and the plurality of lower transistors ( figure 31
elements 192, 194, 196, 111, 112 are respectively offset);
a first frontside gate cut dielectric pillar ( figure 31 element 220) located
adjacent to and parallel to a first nanodevice of the plurality of nanodevices
along an x-axis, wherein a backside surface of the first frontside gate cut
dielectric pillar extends a first width along a y-axis ( par 69; figure 31:
element 220 has a bottom and therefore a bottom width); and
a first backside dielectric fill ( figure 31 elements 155 and 160 in
combination) in direct contact with the backside surface of the first frontside
gate cut dielectric pillar ( par 69: "...the bottom section of the shared upper
gate cut 220 is in direct contact with the bonding oxide 160."), wherein a
frontside surface of the first backside dielectric fill extends a second width along
the y-axis, and wherein the second width is greater than the first width (
figure 31: the frontside surface of element 160 is the frontside surface of the first
backside dielectric fill, that has a larger width in the cross section of figure 31
than the width of the bottom surface of element 220).
Dependent claims 2-5, 9-12, 17-21, 24:
- claims 2, 10 (figure 31 shows that element 194 is closer to element 220
than element 111),
- claims 3, 11, 20 ( figure 31: elements 192, 194, 196 (upper nanosheets)
and elements 111, 112 (lower nanosheets) are laterally offset),
- claims 4, 12, 21 (figure 31: first frontside dielectric liner element 230
extends along inner sidewalls of the plurality of nanosheets, because the
arrangement shown in figure 31 element 230 is laterally repeated; therefore an adjacent element 230 extends along a second inner sidewall of the plurality
of nanosheets and element 220 is formed in between these liners elements 230;
element 220 is a frontside dielectric fill as par 69 discloses "a trench is filled with
a dielectric material to form a shared upper gate cut 220"),
- claim 5 (figure 31: the backside gate cut dielectric pillar element 155 in
combination with element 160 is in direct contact with the backside, i.e. the
bottom part of element 220 (see par 69: ..."the bottom section of the shared
upper gate cut 220 is in direct contact with the bonding oxide 160.")),
- claim 9 (par 52 discloses that "one or more offset stacked devices" are
comprised, i.e. the arrangement of shown in figure 31 is laterally repeated;
consequently figure 31 in combination with par 52 discloses that a further frontside gate cut dielectric pillar element 220 exists left and right of the shown
cross section in figure 31; for the same reasons the structure 155/160 is laterally
repeated and therefore further, i.e. a second backside dielectric fill element, is
formed left and right of the shown cross section in figure 31
- claim 17 (figure 30: element 185 is the upper source/drain (see par 60);
element 140 is the lower source/drain (see par 56);
- claim 18 (figure 30: upper source/drains element 185 and lower source/
drains element 140 are offset;
- claim 19 (figure 31: the upper active regions includes a plurality of upper
nanosheet element 192 and lower nanosheet elements 111; figure 31 shows
that element 192 is laterally closer to element 220 than element 111),
- claim 24 (figure 30 shows an upper source drain region element 185
connected to an upper source/drain contact (element 250 connected to element
185) and a lower source drain region element 140 connected to a lower source/
drain contact (element 250 connected to element 140;
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al as applied to claim 24 above, and further in view of Ping et al
Xie fails to teach:
25. The semiconductor device of claim 24, wherein the upper source/drain contact extends downwards from a backside of the plurality of nanodevices to connect to a backside of the upper source/drain, and wherein the lower source/drain contact extends upwards from a frontside of the plurality of nanodevices to connect to a frontside of the lower source/drain.
Ping teaches:
- (figures 1, 2A disclose stacked gate-all-around nanosheet transistor structure with an upper source/drain element 124 and a lower source/ drain element 113, which are both contacted by respective source drain contacts element 166b and 162 from top side and by contact elements 1644VB and 166TVD from the bottom side; the person-skilled-in-the-art would combine Xie and Ping, because both documents are in the field of stacked gate-all-around nanosheet transistors and would realize that the contact arrangement to the respective source-drain regions in (up and down) would also result in a more routing possibilities and therefore would integrate this routing also in the arrangement of Xie.
Allowable Subject Matter
Claim 6-8, 13-16 and 22, 23 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
6. The semiconductor device of claim 5, wherein the first frontside dielectric liner, the second frontside dielectric liner, the first frontside gate cut dielectric pillar, and the backside gate cut dielectric pillar are comprised of a same dielectric material, and wherein the first backside dielectric fill and the frontside dielectric fill are comprised of a different dielectric material.
13. The semiconductor device of claim 12, further comprising:
a backside gate cut dielectric pillar in direct contact with a backside surface of the frontside dielectric fill; and
a first backside dielectric liner and a second backside dielectric liner located along an inner sidewall of the second backside dielectric fill and an inner sidewall of the first backside dielectric fill, respectively, wherein the first frontside dielectric liner and the second backside dielectric liner are offset from each other across the plurality of upper transistors and the plurality of lower transistors, and wherein the second frontside dielectric liner and the first backside dielectric liner are offset from each other across the plurality of upper transistors and the plurality of lower transistors.
22. The semiconductor device of claim 21, further comprising:
a backside gate cut dielectric pillar in direct contact with a backside surface of the frontside dielectric fill; and
a first backside dielectric liner and a second backside dielectric liner located along an inner sidewall of the second backside dielectric fill and an inner sidewall of the first backside dielectric fill, respectively, wherein the first frontside dielectric liner and the second backside dielectric liner are offset from each other across the plurality of upper transistors and the plurality of lower transistors, and wherein the second frontside dielectric liner and the first backside dielectric liner are offset from each other across the plurality of upper transistors and the plurality of lower transistors.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Xie et al, US 20230335585 also teaches the invention as claimed.
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/Primary Examiner, Art Unit 2893