Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of invention I, claims 1-10 in the reply filed on 07/27/2026 is acknowledged. The traversal is on the ground(s) that there is no serious burden because the claimed inventions overlap in scope and have common elements such as “a horizontal channel, an interlayer insulating layer, a vertical channel structure, etc.), and that by searching for one group, the other would naturally be found if there is art. This is not found persuasive because while there is some overlap in scope, it is still apparent that inventions I and II are distinct. As pointed out in the restriction requirement dated 05/29/2026, there is a search burden as invention I would require searching devices using the same style of field effect transistor, whereas the device from invention II would not require this search. Yes, during search there may be some overlap in scope, however, both inventions still require their own areas of search that the other does not require.
The requirement is still deemed proper and is therefore made FINAL.
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention II, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 07/27/2026.
Drawings
The drawings are objected to because in brief description of drawings Fig 10 is supposed to be based on the B1-B1’ dashed line from Fig. 9. However, B1-B1’ in Fig. 9 is not a line and more of an L-Shape. The B1 or B1’ appear mislabeled or misplaced, based on the fact that Fig. 10 has the Con region and the MCR region. Examiner assumes that the dashed line is supposed to follow only the labeled x-axis and more horizontally across Fig. 9.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by United states Patent Application Publication by Hwang et al. (US 20170047342 A1; Hwang).
Regarding claim 1, Hwang discloses a field effect transistor comprising:
a horizontal channel layer (SP - 140, Figs. 4, 10B, 11A, where the region where channel region 140 extends horizontally, Para. 66);
an interlayer insulating layer (121) on the horizontal channel layer (Para. 73, Fig. 10B where the interlayer insulating layer 121 is on the horizontal channel layer 140);
a gate electrode layer (131) on the interlayer insulating layer (Para. 69, Fig. 10B where the gate electrode layer 131 is on interlayer insulating layer);
a first vertical channel structure (Para. 66, Fig. 10B/11A, Left vertical structure including vertical channel in channel holes CH under channel pads 172) passing through the gate electrode layer and the interlayer insulating layer in a vertical direction (Fig. 10B/11A, Where the left structure under pad 172, passes through interlayer insulating layer 121 and gate electrode layer 131), in contact with the horizontal channel layer (Para 66, “a channel region 140 disposed in the channel holes CH”), and connected to one of a source terminal or a drain terminal (Para. 82, “The first channel pads 172 may act as drain regions of string select transistors SST”); and
a second vertical channel structure (Para. 66, Fig. 11A, vertical structure including vertical channel in channel holes CH under channel pads 174) apart from the first vertical channel structure in a horizontal direction, passing through the gate electrode layer and the interlayer insulating layer in the vertical direction (Fig. 11A, Where the structure under pad 174, passes through interlayer insulating layer 121 and gate electrode layer 131), in contact with the horizontal channel layer (Para 66, “a channel region 140 disposed in the channel holes CH”), and connected to another of the source terminal or the drain terminal (Para. 109, “Thus, the second channel pads 174 connected to the common source line CSL need not be disposed at upper ends of the channel holes CH”).
Regarding claim 2, Hwang discloses the field effect transistor of claim 1, wherein the horizontal channel layer includes:
a first portion (portion of SP - Fig. 5, where the bottom of the vertical channel structures are disposed over the horizontal channel layer and the horizontal channel layer, and the first portion may be any chosen portion of SP/140) at least partially overlapping the first vertical channel structure in the vertical direction (Figs. 4,5 where here we will choose the first portion to be a portion of the horizontal channel layer SP/140 that is directly under the vertical channel structure 172, but slightly larger area in the horizontal direction [xy plane] then the first vertical channel structure, ie. Circular with a larger radius); and
a second portion (portion SP - Fig. 5, where the bottom of the vertical channel structures are disposed over the horizontal channel layer and the horizontal channel layer, and the first portion may be any chosen portion of SP/140) at least partially overlapping the second vertical channel structure in the vertical direction (Figs. 4,5 where here we will choose the first portion to be a portion of the horizontal channel layer SP/140 that is directly under the vertical channel structure 174, but slightly larger area in the horizontal direction [xy plane] then the first vertical channel structure, ie. Circular with a larger radius),
wherein, in a plan view, the first portion has a greater planar area than a lower surface of the first vertical channel structure, and the second portion has a greater planar area than a lower surface of the second vertical channel structure (The chosen first and second portions as described above, will have a greater planar area [xy plane] in plan view then the corresponding vertical channel structures above them).
Regarding claim 3, Hwang discloses the field effect transistor of claim 1, wherein the horizontal channel layer includes:
a first portion (portion of SP - Fig. 5, where the bottom of the vertical channel structures are disposed over the horizontal channel layer and the horizontal channel layer, and the first portion may be any chosen portion of SP/140) at least partially overlapping the first vertical channel structure in the vertical direction (Figs. 4,5 where here we will choose the first portion to be a portion of the horizontal channel layer SP/140 that is directly under the vertical channel structure 172, but slightly larger area in the horizontal direction [xy plane] then the first vertical channel structure, ie. Circular with a larger radius); and
a second portion (portion SP - Fig. 5, where the bottom of the vertical channel structures are disposed over the horizontal channel layer and the horizontal channel layer, and the first portion may be any chosen portion of SP/140) at least partially overlapping the second vertical channel structure in the vertical direction (Figs. 4,5 where here we will choose the first portion to be a portion of the horizontal channel layer SP/140 that is directly under the vertical channel structure 174, but slightly larger area in the horizontal direction [xy plane] then the first vertical channel structure, ie. Circular with a larger radius),
wherein each of the first portion and the second portion has a circular planar shape (In plan view, the chosen first and second portions of the horizontal channel layer SP/140 are circular in shape), and in a plan view, the horizontal channel layer has a planar shape in which a circle of the first portion and a circle of the second portion at least partially overlap each other (When choosing first and second portions of the horizontal channel layer SP/140, the portions are large enough in diameter that they overlap in their area in plan view).
Regarding claim 4, Hwang discloses the field effect transistor of claim 1, wherein the horizontal channel layer includes:
a first portion (portion of SP - Fig. 5, where the bottom of the vertical channel structures are disposed over the horizontal channel layer and the horizontal channel layer, and the first portion may be any chosen portion of SP/140) at least partially overlapping the first vertical channel structure in the vertical direction (Figs. 4,5 where here we will choose the first portion to be a portion of the horizontal channel layer SP/140 that is directly under the vertical channel structure 172, but slightly larger area in the horizontal direction [xy plane] then the first vertical channel structure, ie. Circular with a larger radius); and
a second portion (portion SP - Fig. 5, where the bottom of the vertical channel structures are disposed over the horizontal channel layer and the horizontal channel layer, and the first portion may be any chosen portion of SP/140) at least partially overlapping the second vertical channel structure in the vertical direction (Figs. 4,5 where here we will choose the first portion to be a portion of the horizontal channel layer SP/140 that is directly under the vertical channel structure 174, but slightly larger area in the horizontal direction [xy plane] then the first vertical channel structure, ie. Circular with a larger radius),
wherein in a plan view, the first vertical channel structure and the first portion have a concentric circular shape, and the second vertical channel structure and the second portion have a concentric circular shape (Para. 78, Fig. 5, where each of the chosen regions are circular in shape and the vertical portions are circular in shape).
Regarding claim 5, Hwang discloses the field effect transistor of claim 1, further comprising:
a third vertical channel structure (Fig. 11B, the vertical structure under contact plug 176 or under the second contact plug 172) apart from the first vertical channel structure and the second vertical channel structure in the horizontal direction, passing through the gate electrode layer and the interlayer insulating layer in the vertical direction, and in contact with the horizontal channel layer (Fig. 11B, Para. 84).
Regarding claim 6, Hwang discloses the field effect transistor of claim 5, wherein
the first vertical channel structure includes a first vertical channel layer contacting the horizontal channel layer, and a first conductive plug (172) on the first vertical channel layer (Para. 82, 130, and Fig. 11A, where the horizontal channel layer 140 also extends into the first vertical structure),
the second vertical channel structure includes a second vertical channel layer contacting the horizontal channel layer, and a second conductive plug (174) on the second vertical channel layer (Para. 83, 130, and Fig. 11A, where the horizontal channel layer 140 also extends into the second vertical structure),
the third vertical channel structure includes, a third vertical channel layer contacting the horizontal channel layer, and a third conductive plug (172 – the other one in Fig. 11A) on the third vertical channel layer (Para. 82, 130, and Fig. 11A, where the horizontal channel layer 140 also extends into the third vertical structure), and
the first conductive plug, the second conductive plug, and the third conductive plug include dopants having a same conductivity type (Para. 82, where the first and third conductive plugs 172 are of the first conductivity-type, And Para. 83, where second conductive plug 174 is also the first conductivity-type).
Regarding claim 7, Hwang discloses the field effect transistor of claim 5, wherein
the first vertical channel structure includes a first vertical channel layer contacting the horizontal channel layer, and a first conductive plug (172) on the first vertical channel layer (Para. 82, 130, and Fig. 11A, where the horizontal channel layer 140 also extends into the first vertical structure),
the second vertical channel structure includes a second vertical channel layer contacting the horizontal channel layer, and a second conductive plug (174) on the second vertical channel layer (Para. 83, 130, and Fig. 11A, where the horizontal channel layer 140 also extends into the second vertical structure),
the third vertical channel structure includes, a third vertical channel layer contacting the horizontal channel layer, and a third conductive plug (176) on the third vertical channel layer (Para. 84, 130, and Fig. 11A, where the horizontal channel layer 140 also extends into the third vertical structure), and
each of the first conductive plug and the second conductive plug includes a dopant having a first conductivity type, and the third conductive plug includes a dopant having a second conductivity type which is opposite to the first conductivity type (Para. 82, where the first conductive plug 172 and Para. 83, where second conductive plug 174 are the first conductivity-type. Para. 83 where the third conductive plug 176 is a second conductivity-type).
Claims 1, and 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by United states Patent Application Publication by Cho et al. (US 20180308856 A1; Cho).
Regarding claim 1, Cho discloses a field effect transistor comprising:
a horizontal channel layer (HC – Fig. 3B);
an interlayer insulating layer (122P) on the horizontal channel layer (Para. 25-26, and Fig. 3B);
a gate electrode layer (EL) on the interlayer insulating layer (Para. 25, and Fig. 3B);
a first vertical channel structure (VC – Fig. 2) passing through the gate electrode layer and the interlayer insulating layer in a vertical direction (Para. 28, Fig. 3B, where the first vertical channel VC penetrates the interlayer insulating layer 122P and the gate electrode layer EL in the vertical direction which is vertical in the fig also called D3 by reference), in contact with the horizontal channel layer (Para. 28, 30), and connected to one of a source terminal or a drain terminal (Para. 31 and 69); and
a second vertical channel structure (VC – Any other VC that is in the same D2 direction as the first vertical channel structure VC) apart from the first vertical channel structure in a horizontal direction (Para. 29, and Figs. 3A-3C), passing through the gate electrode layer and the interlayer insulating layer in the vertical direction (Para. 28, Fig. 3B, where the any of the vertical channel VC penetrates the interlayer insulating layer 122P and the gate electrode layer EL in the vertical direction which is vertical in the fig also called D3 by reference), in contact with the horizontal channel layer (Para. 28, 30), and connected to another of the source terminal or the drain terminal (Para. 31 and 69).
Regarding claim 8, Cho discloses the field effect transistor of claim 1, further comprising:
a dummy vertical channel structure (DVC) between the first vertical channel structure and the second vertical channel structure to be apart from the first vertical channel structure and the second vertical channel structure in the horizontal direction (Para. 39, and Fig. 2, where the vertical channel structures are ordered in a manner which some of the groups vertical channels in the D2 [horizontal] direction will have a dummy vertical channel between other vertical channels) and passing through the gate electrode layer and the interlayer insulating layer in the vertical direction to be in contact with the horizontal channel layer (Para. 32, “The dummy vertical channels DVC may have the same structure as that of the vertical channels VC. For example, the dummy vertical channels DVC may have bottom ends connected to the horizontal channel HC”).
Regarding claim 9, Cho discloses the field effect transistor of claim 8, wherein the horizontal channel layer includes:
A first portion overlapping the first vertical channel structure in the vertical direction (portion of horizontal channel language HC that is directly under the first vertical channel structure VC);
a second portion overlapping the second vertical channel structure in the vertical direction (portion of horizontal channel language HC that is directly under the second vertical channel structure another VC); and
a fourth portion overlapping the dummy vertical channel structure in the vertical direction (portion of horizontal channel language HC that is directly under the dummy vertical channel DVC),
wherein the fourth portion is between the first portion and the second portion (As we choose a first vertical channel structure and a second vertical channel structure that are on opposite sides of the dummy vertical channel structure, the fourth portion will be between the first and second portions).
Regarding claim 10, Cho discloses the field effect transistor of claim 1, further comprising:
an insulating structure (144) on the horizontal channel layer and facing the gate electrode layer in the horizontal direction (Para. 80, Fig. 3C); and
a body contact (146) passing through the insulating structure and contacting the horizontal channel layer (Para. 44, Fig. 3C).
Conclusion
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/DANIEL J HIBBERT/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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