DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
Applicant’s election of Group I, claims 1-20 in the reply filed on 3/23/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Group II, claims 21-25 are withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 11/14/2023 and IDS filed on 1/22/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDSs are considered by the examiner.
Claim Objections
Claim 17 is objected to because of the following informalities:
In claim 17, line 11, “the first and second corresponding edges of the first and second active” should read --the first corresponding edges of the first and second active-- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chae et al. (US 2014/0353768; hereinafter ‘Chae’) in view of Vashishtha (A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy, Arizona State University, 2019).
Regarding claim 1, Chae teaches a field effect transistor (FET) device (Figs. 1A-1C, [0013]), comprising:
an active region (ACT, [0055]) comprising a source (122, [0059]) at a first end of the active region (the left end of ACT, Fig. 1C) and a drain (124) at a second end of the active region (the right end of ACT); and
a gate (110, [0056]) extending across the active region (ACT) and comprising at least one end extending past a corresponding edge of the active region (L1 and L2 extending past ACT, Fig. 1B).
Chae does not teach that the gate extends past the active region by a sub-lithographic dimension.
Vashishtha teaches that a gate extends past an active region by a sub-lithographic dimension (a vertical endcap of 4 nm past the active region, p. 51, 4.3 Standard Cell MOL Usage).
As taught by Vashishtha, one of ordinary skill in the art would utilize and modify the above teaching into Chae to obtain and achieve that the gate extends past the active region by a sub-lithographic dimension as claimed, because sufficient separation is maintained to prevent reliability degradation such as time-dependent dielectric breakdown (TDDB) (p. 7, 2.1.4 Time-Dependent Dielectric Breakdown (TDDB)), and such separation is achieved by extending gate structure (e.g., through a gate cap and spacers) (p. 25, 3.1 Front End of Line (FEOL) and Middle of Line (MOL) Layers), while accounting for process variability such as edge placement error, which requires nanometer-scale margins (p. 26, 3.1 FEOL and MOL Layers), thereby resulting in a sub-lithographic dimension.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Vashishtha in combination with Chae due to above reason.
Regarding claim 2, Chae in view of Vashishtha teaches the FET device according to claim 1, wherein:
the gate comprises the at least one end extending past the corresponding edge of the active region (Chae: 110 includes portion L1 and L2 extending past ACT, Fig. 1B), and
a contact (135, Fig. 1B, [0060]) is disposed in contact with a second end of the gate (the end of 110 corresponding to L1) at an exterior of the active region (outside ACT).
Chae does not teach that the gate extends past the active region by a sub-lithographic dimension.
Vashishtha teaches that the gate extends past the active region by a sub-lithographic dimension (a vertical endcap of 4 nm past the active region, p. 51, 4.3 Standard Cell MOL Usage).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Vashishtha to obtain and achieve that the gate extends past the active region by a sub-lithographic dimension as claimed, because sufficient separation is maintained to prevent reliability degradation such TDDB (p. 7, 2.1.4 TDDB), and such separation is achieved by extending gate structure (e.g., through a gate cap and spacers) (p. 25, 3.1 FEOL and MOL Layers), while accounting for process variability such as edge placement error, which requires nanometer-scale margins (p. 26, 3.1 FEOL and MOL Layers), thereby resulting in a sub-lithographic dimension.
Regarding claim 3, Chae in view of Vashishtha teaches the FET device according to claim 2, further comprising a spacer (Chae: the left spacer 119, Fig. 1B, [0059]) contacting the one end of the gate (the left end of 110).
Regarding claim 4, Chae in view of Vashishtha teaches the FET device according to claim 1, wherein:
the gate comprises opposite ends respectively extending past corresponding edges of the active region (Chae: 110 includes portion L1 and L2 extending past ACT, Fig. 1B), and
a contact (135, Fig. 1B, [0060]) is disposed in contact with the gate (110) within a footprint of the active region (inside ACT).
Chae does not teach that the gate extends past the active region by a sub-lithographic dimension.
Vashishtha teaches that the gate extends past the active region by a sub-lithographic dimension (a vertical endcap of 4 nm past the active region, p. 51, 4.3 Standard Cell MOL Usage).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Vashishtha to obtain and achieve that the gate extends past the active region by a sub-lithographic dimension as claimed, because sufficient separation is maintained to prevent reliability degradation such TDDB (p. 7, 2.1.4 TDDB), and such separation is achieved by extending gate structure (e.g., through a gate cap and spacers) (p. 25, 3.1 FEOL and MOL Layers), while accounting for process variability such as edge placement error, which requires nanometer-scale margins (p. 26, 3.1 FEOL and MOL Layers), thereby resulting in a sub-lithographic dimension.
Regarding claim 5, Chae in view of Vashishtha teaches the FET device according to claim 4, further comprising spacers (Chae: 119, Fig. 1B, [0059]) respectively contacting the opposite ends of the gate (the opposite ends of 110).
Regarding claim 6, Chae in view of Vashishtha teaches the FET device according to claim 1, Chae does not teach the FET device wherein the sub-lithographic dimension is 5 nm or less along a longitudinal axis of the gate.
Vashishtha teaches that the sub-lithographic dimension is 5 nm or less along a longitudinal axis of the gate (a vertical endcap of 4 nm past the active region, p. 51, 4.3 Standard Cell MOL Usage).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Vashishtha to obtain and the FET device wherein the sub-lithographic dimension is 5 nm or less along a longitudinal axis of the gate as claimed, because it has been held that where the criticality of the claimed range is not shown and the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In reWertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP § 2144.05.
Regarding claim 9, Chae teaches a field effect transistor (FET) device (Figs. 1A-1C, [0013]), comprising:
an active region (ACT, [0055]) comprising a source (122, [0059]) at a first end of the active region (the left end of ACT, Fig. 1C) and a drain (124) at a second end of the active region (the right end of ACT);
a gate (110, [0056]) extending transversely across the active region (ACT) and comprising first (the end of 110 corresponding to L1; hereinafter ‘110L1’) and second (the end of 110 corresponding to L2; hereinafter ‘110L2’) opposite ends respectively extending past a corresponding edges of the active region (110L1 and 110L2 extending past ACT, Fig. 1B);
a contact (135, Fig. 1B, [0060]) disposed in contact with the gate (110) within a footprint of the active region (inside ACT); and
first (the left spacer 119, Fig. 1B, [0059]; hereinafter ‘119L1’) and second spacers (the right spacer 119; hereinafter ‘119L2’) respectively contacting the first (110L1) and second ends of the gate (110L2).
Chae does not teach that the gate extends past the active region by a sub-lithographic dimension.
Vashishtha teaches that a gate extends past an active region by a sub-lithographic dimension (a vertical endcap of 4 nm past the active region, p. 51, 4.3 Standard Cell MOL Usage).
As taught by Vashishtha, one of ordinary skill in the art would utilize and modify the above teaching into Chae to obtain and achieve that the gate extends past the active region by a sub-lithographic dimension as claimed, because sufficient separation is maintained to prevent reliability degradation such TDDB (p. 7, 2.1.4 TDDB), and such separation is achieved by extending gate structure (e.g., through a gate cap and spacers) (p. 25, 3.1 FEOL and MOL Layers), while accounting for process variability such as edge placement error, which requires nanometer-scale margins (p. 26, 3.1 FEOL and MOL Layers), thereby resulting in a sub-lithographic dimension.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Vashishtha in combination with Chae due to above reason.
Regarding claim 10, Chae in view of Vashishtha teaches the FET device according to claim 9, Chae does not teach the FET device wherein the sub-lithographic dimension is 5 nm or less along a longitudinal axis of the gate.
Vashishtha teaches that the sub-lithographic dimension is 5 nm or less along a longitudinal axis of the gate (a vertical endcap of 4 nm past the active region, p. 51, 4.3 Standard Cell MOL Usage).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Vashishtha to obtain and the FET device wherein the sub-lithographic dimension is 5 nm or less along a longitudinal axis of the gate as claimed, because it has been held that where the criticality of the claimed range is not shown and the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In reWertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP § 2144.05.
Claims 7-8 and 11-12, are rejected under 35 U.S.C. 103 as being unpatentable over Chae (US 2014/0353768) in view of Vashishtha (A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy, Arizona State University, 2019), and further in view of Frougier et al. (US 2022/0231020; hereinafter ‘Frougier’).
Regarding claim 7, Chae in view of Vashishtha teaches the FET device according to claim 1, but does not teach the FET device wherein the gate comprises a replacement metal gate.
Frougier teaches a FET device (FIGS. 11A-11C, [0004]) wherein the gate comprises a replacement metal gate (the gate trenches and gaps enable formation of replacement metal gates, [0140]).
As taught by Frougier, one of ordinary skill in the art would utilize and modify the above teaching into Chae in view of Vashishtha to obtain and achieve the FET device wherein the gate comprises a replacement metal gate as claimed, because forming the replacement metal gate enables the gate to surround the nanosheet channels, thereby improving control of the channel region [0003, 0140].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Frougier in combination with Chae in view of Vashishtha due to above reason.
Regarding claim 8, Chae in view of Vashishtha and Frougier teaches the FET device according to claim 7, but Chae in view of Vashishtha does not teach the FET device wherein the replacement metal gate comprises one of tungsten and aluminum.
Frougier teaches the FET device wherein the replacement metal gate comprises one of tungsten and aluminum (the gate electrode of the replacement metal gate is made of tungsten or aluminum, [0143]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Frougier to obtain and achieve the FET device wherein the replacement metal gate comprises one of tungsten and aluminum as claimed, because tungsten and aluminum are suitable conductive materials for forming gate electrodes in semiconductor devices. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 11, Chae in view of Vashishtha teaches the FET device according to claim 9, but does not teach the FET device wherein the gate comprises a replacement metal gate.
Frougier teaches a FET device (FIGS. 11A-11C, [0004]) wherein the gate comprises a replacement metal gate (the gate trenches and gaps enable formation of replacement metal gates, [0140]).
As taught by Frougier, one of ordinary skill in the art would utilize and modify the above teaching into Chae in view of Vashishtha to obtain and achieve the FET device wherein the gate comprises a replacement metal gate as claimed, because forming the replacement metal gate enables the gate to surround the nanosheet channels, thereby improving control of the channel region [0003, 0140].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Frougier in combination with Chae in view of Vashishtha due to above reason.
Regarding claim 12, Chae in view of Vashishtha and Frougier teaches the FET device according to claim 11, but Chae in view of Vashishtha does not teach the FET device wherein the replacement metal gate comprises one of tungsten and aluminum.
Frougier teaches the FET device wherein the replacement metal gate comprises one of tungsten and aluminum (the gate electrode of the replacement metal gate is made of tungsten or aluminum, [0143]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Frougier to obtain and achieve the FET device wherein the replacement metal gate comprises one of tungsten and aluminum as claimed, because tungsten and aluminum are suitable conductive materials for forming gate electrodes in semiconductor devices. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chae (US 2014/0353768) in view of Vashishtha (A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy, Arizona State University, 2019), and further in view of Blatchford (US 2012/0331425).
Regarding claim 13, Chae teaches a field effect transistor (FET) device (Figs. 1A-1C, [0013]), comprising:
an active region (ACT, [0055]) comprising a source (124, [0059]) at a first end of the active region (the right end of ACT, Fig. 1C; hereinafter ‘ACTL2’) and a drain (122) at a second end of the active region (the left end of ACT; hereinafter ‘ACTL1’);
a gate (110, [0056]) extending transversely across the active region (ACT) and comprising first (the end of 110 corresponding to L2; hereinafter ‘110L2’) and second (the end of 110 corresponding to L1; hereinafter ‘110L1’) opposite ends, the first end (110L2) extending past a first corresponding edge of the active region (ACTL2) and the second end (110L1) extending past a second corresponding edge of the active region (ACTL1);
a contact (135, Fig. 1B, [0060]) disposed in contact with the second end of the gate (110L1) at an exterior of the active region (outside ACT); and
a spacer (the right spacer 119; hereinafter ‘119L2’) contacting the first ends of the gate (110L2).
Chae does not teach that the first gate end extends past the first edge of the active region by a sub-lithographic dimension and the second gate end extends past the second edge of the active region in excess of the sub-lithographic dimension.
Vashishtha teaches that the first gate end extends past the first edge of the active region by a sub-lithographic dimension (a vertical endcap of 4 nm past the active region, p. 51, 4.3 Standard Cell MOL Usage).
As taught by Vashishtha, one of ordinary skill in the art would utilize and modify the above teaching into Chae to obtain and achieve that the first gate end extends past the first edge of the active region by a sub-lithographic dimension as claimed, because sufficient separation is maintained to prevent reliability degradation such TDDB (p. 7, 2.1.4 TDDB), and such separation is achieved by extending gate structure (e.g., through a gate cap and spacers) (p. 25, 3.1 FEOL and MOL Layers), while accounting for process variability such as edge placement error, which requires nanometer-scale margins (p. 26, 3.1 FEOL and MOL Layers), thereby resulting in a sub-lithographic dimension.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Vashishtha in combination with Chae due to above reason.
Chae in view of Vashishtha does not teach that the second gate end extends past the second edge of the active region in excess of the sub-lithographic dimension.
Blatchford teaches that the second gate end extends past the second edge of the active region in excess of the sub-lithographic dimension (a gate line end extends past an edge of an underlying active area, for example 25 nm, [0025]).
As taught by Blatchford, one of ordinary skill in the art would utilize and modify the above teaching into Chae in view of Vashishtha to obtain and achieve that the second gate end extends past the second edge of the active region in excess of the sub-lithographic dimension as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Blatchford in combination with Chae in view of Vashishtha due to above reason.
Regarding claim 14, Chae in view of Vashishtha and Blatchford teaches the FET device according to claim 13, Chae in view of Blatchford does not teach the FET device wherein the sub-lithographic dimension is 5 nm or less along a longitudinal axis of the gate.
Vashishtha teaches that the sub-lithographic dimension is 5 nm or less along a longitudinal axis of the gate (a vertical endcap of 4 nm past the active region, p. 51, 4.3 Standard Cell MOL Usage).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Vashishtha to obtain and the FET device wherein the sub-lithographic dimension is 5 nm or less along a longitudinal axis of the gate as claimed, because it has been held that where the criticality of the claimed range is not shown and the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In reWertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP § 2144.05.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Chae (US 2014/0353768) in view of Vashishtha (A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy, Arizona State University, 2019) and Blatchford (US 2012/0331425), and further in view of Frougier (US 2022/0231020).
Regarding claim 15, Chae in view of Vashishtha and Blatchford teaches the FET device according to claim 13, but does not teach the FET device wherein the gate comprises a replacement metal gate.
Frougier teaches a FET device (FIGS. 11A-11C, [0004]) wherein the gate comprises a replacement metal gate (the gate trenches and gaps enable formation of replacement metal gates, [0140]).
As taught by Frougier, one of ordinary skill in the art would utilize and modify the above teaching into Chae in view of Vashishtha and Blatchford to obtain and achieve the FET device wherein the gate comprises a replacement metal gate as claimed, because forming the replacement metal gate enables the gate to surround the nanosheet channels, thereby improving control of the channel region [0003, 0140].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Frougier in combination with Chae in view of Vashishtha and Blatchford due to above reason.
Regarding claim 16, Chae in view of Vashishtha, Blatchford, and Frougier teaches the FET device according to claim 15, but Chae in view of Vashishtha and Blatchford does not teach the FET device wherein the replacement metal gate comprises one of tungsten and aluminum.
Frougier teaches the FET device wherein the replacement metal gate comprises one of tungsten and aluminum (the gate electrode of the replacement metal gate is made of tungsten or aluminum, [0143]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Frougier to obtain and achieve the FET device wherein the replacement metal gate comprises one of tungsten and aluminum as claimed, because tungsten and aluminum are suitable conductive materials for forming gate electrodes in semiconductor devices. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Vashishtha (A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy, Arizona State University, 2019) in view of Blatchford (US 2012/0331425), Li et al. (CN 115796103A; hereinafter ‘Li’), and Chae (US 2014/0353768).
Regarding claim 17, Vashishtha teaches a field effect transistor (FET) device (Fig. 4.1, p. 45, 4.1 Gear Ratio and Cell Height), comprising:
first (the upper-left active region; hereinafter ‘A1’), and second active regions (the lower-left active region; hereinafter ‘A2’), each comprising a source (an SD region formed in an active region adjacent to a first side of the gate, Fig. 3.1, corresponding to an active region adjacent to the gate in Fig. 4.1, p. 26, 3.1 Front End of Line (FEOL) and Middle of Line (MOL) Layers; hereinafter ‘S’) at a first end thereof (the left end of the active region) and a drain (an SD region formed in an active region adjacent to an opposite side of the gate; hereinafter ‘D’) at a second end thereof (the right end of the active region); and
first (the first gate disposed above the LIG feature that is second from a right side, p. 27, 3.1 Front End of Line (FEOL) and Middle of Line (MOL) Layers; hereinafter ‘G1’) and second gates (the second gate disposed below the LIG feature that is second from a right side; hereinafter ‘G2’) extending transversely across the first (A1) and second active regions (A2), respectively, each of the first (G1) and second gates (G2) comprising complementary first ends (the inner portion of G1 and G2; hereinafter ‘G1E1’ and ‘G2E1’) extending past first corresponding edges of the first (the edge of A1 adjacent to LIG; hereinafter ‘A1E1’) and second active regions (the edge of A2 adjacent to LIG; hereinafter ‘A2E1’) by a sub-lithographic dimension (a vertical endcap of 4 nm past the active region, p. 51, 4.3 Standard Cell MOL Usage) and complementary second ends (the inner portion of G1 and G2; hereinafter ‘G1E2’) extending past second corresponding edges of the first (the edge of A1 adjacent to the power rail; hereinafter ‘A1E2’) and second active regions (the edge of A2 adjacent to the power rail; hereinafter ‘A2E2’);
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a contact (LIG) disposed in contact with the complementary first ends of the first (G1E1) and second gates (G2E1).
Vashishtha does not teach the FET device comprising: the second gate ends extend past second corresponding edges of the first and second active regions in excess of the sub-lithographic dimension; the contact disposed in contact with the first and second corresponding edges of the first and second active regions; first spacers contacting the complementary first ends of the first and second gates; and second spacers contacting the complementary second ends of the first and second gates.
Blatchford teaches that the second gate ends extend past second corresponding edges of the first and second active regions in excess of the sub-lithographic dimension (a gate line end extends past an edge of an underlying active area, for example 25 nm, [0025]).
As taught by Blatchford, one of ordinary skill in the art would utilize and modify the above teaching into Vashishtha to obtain and achieve that the second gate end extends past the second edge of the active region in excess of the sub-lithographic dimension as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Blatchford in combination with Vashishtha due to above reason.
Vashishtha in view of Blatchford does not teach the FET device comprising: the contact disposed in contact with the first and second corresponding edges of the first and second active regions; first spacers contacting the complementary first ends of the first and second gates; and second spacers contacting the complementary second ends of the first and second gates.
Li teaches a transistor device (FIG. 1, [0048]) comprising a contact (1401, [0049]) disposed in contact with the first and second corresponding edges of the first (one edge of 1201) and second active regions (one edge of 1202).
As taught by Li, one of ordinary skill in the art would utilize and modify the above teaching into Vashishtha in view of Blatchford to obtain and achieve the transistor device comprising the contact disposed in contact with the first and second corresponding edges of the first and second active regions as claimed, because directly interconnecting the active regions reduces the use of metal routing, simplifies the interconnect structure, and improves layout efficiency and device integration [0056].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Li in combination with Vashishtha in view of Blatchford due to above reason.
Vashishtha in view of Blatchford and Li does not teach the FET device comprising: first spacers contacting the complementary first ends of the first and second gates; and second spacers contacting the complementary second ends of the first and second gates.
Chae teaches a FET device (Figs. 8A and 8B, [0013]) comprising: first spacers (the right spacer 319 of 310d and the left spacer 319 of 310b, [0155]) contacting the complementary first ends of the first (the side of 310d adjacent to Va, [0161]) and second gates (the side of 310b adjacent to Va); and second spacers (the left spacer 319 of 310d and the right spacer 319 of 310b) contacting the complementary second ends of the first (the side of 310d opposite Va) and second gates (the side of 310b opposite Va).
As taught by Chae, one of ordinary skill in the art would utilize and modify the above teaching into Vashishtha in view of Blatchford and Li to obtain and achieve the FET device comprising: first spacers contacting the complementary first ends of the first and second gates; and second spacers contacting the complementary second ends of the first and second gates as claimed, because spacers are conventionally provided o sidewalls of gate electrodes to electrically isolate the gate and to enable self-aligned formation of source/drain regions [0059].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chae in combination with Vashishtha in view of Blatchford and Li due to above reason.
Regarding claim 18, Vashishtha in view of Blatchford, Li, and Chae teaches the FET device according to claim 17, wherein the sub-lithographic dimension is 5 nm or less along a longitudinal axis of each of the first and second (Vashishtha: a vertical endcap of 4 nm past the active region, p. 51, 4.3 Standard Cell MOL Usage).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Vashishtha (A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy, Arizona State University, 2019) in view of Blatchford (US 2012/0331425), Li (CN 115796103A), and Chae (US 2014/0353768), and further in view of Frougier (US 2022/0231020).
Regarding claim 19, Vashishtha in view of Blatchford, Li, and Chae teaches the FET device according to claim 17, but does not teach the FET device wherein the first and second gates each comprises a replacement metal gate.
Frougier teaches a FET device (FIGS. 11A-11C, [0004]) wherein the gate comprises a replacement metal gate (the gate trenches and gaps enable formation of replacement metal gates, [0140]).
As taught by Frougier, one of ordinary skill in the art would utilize and modify the above teaching into Vashishtha in view of Blatchford, Li, and Chae to obtain and achieve the FET device wherein the first and second gates each comprises a replacement metal gate as claimed, because forming the replacement metal gate enables the gate to surround the nanosheet channels, thereby improving control of the channel region [0003, 0140].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Frougier in combination with Vashishtha in view of Blatchford, Li, and Chae due to above reason.
Regarding claim 20, Vashishtha in view of Blatchford, Li, Chae, and Frougier teaches the FET device according to claim 19, but Vashishtha in view of Blatchford, Li, and Chae does not teach the FET device wherein the replacement metal gate comprises one of tungsten and aluminum.
Frougier teaches the FET device wherein the replacement metal gate comprises one of tungsten and aluminum (the gate electrode of the replacement metal gate is made of tungsten or aluminum, [0143]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Frougier to obtain and achieve the FET device wherein the replacement metal gate comprises one of tungsten and aluminum as claimed, because tungsten and aluminum are suitable conductive materials for forming gate electrodes in semiconductor devices. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 4/9/26
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