DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 7/2/2026. Claims 1, 3, 6-8, and 13-20 are pending in this application. Claims 1, 3, 13, and 17 are amended. Claims 2, 4-5, and 9-12 are canceled. Claims 21-25 remain withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Chae et al. (US 2014/0353768; hereinafter ‘Chae’) in view of Vashishtha (A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy, Arizona State University, 2019).
Regarding claim 1, Chae teaches a field effect transistor (FET) device (Figs. 1A-1C, [0013]), comprising:
an active region (ACT, [0055]) comprising a source (122, [0059]) at a first end of the active region (the left end of ACT, Fig. 1C) and a drain (124) at a second end of the active region (the right end of ACT);
a gate (110, [0056]) extending in a first direction across the active region (110 extending in D1 across ACT, Fig. 1A, [0056]) and comprising at least one end extending past a corresponding edge of the active region (L1 and L2 extending past a corresponding edge of ACT, Fig. 1B), the gate having a rectangular shape with a uniform width from end-to-end in a second direction perpendicular to the first direction (110 having a rectangular shape with a uniform width Wg from end-to-end in D2, Fig. 1A, [0058, 0068]); and
a contact (135, Fig. 1A, [0060]) having an annular shape that differs from the rectangular shape of the gate (135 having a circular shape, [0067]) and a diametric width which is less than the uniform width of the gate (the circular contact 135 having a diametric width Wc2 less than Wg of 110, Fig. 1A, [0068]).
Chae does not explicitly teach the FET device wherein the contact is disposed in contact with a second end of the gate such that an entirety of the contact is disposed at an exterior of a footprint of the active region.
Chae, however, provides that a gate contact 1236 contacting an end of a gate 1210 and being disposed entirely outside the footprint of active region ACT1 or ACT2 (Fig. 11, [0126])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Chae to obtain and achieve the FET device wherein the contact is disposed in contact with a second end of the gate such that an entirety of the contact is disposed at an exterior of a footprint of the active region as claimed, because positing the gate contact outside the active region prevents processing chemicals from penetrating through the gate material and deteriorating the underlying gate insulating layer, thereby protecting the gate dielectric and improving device reliability [0092].
Chae does not teach that the gate extends past the active region by a sub-lithographic dimension, wherein: the at least one end extends past the corresponding edge of the active region by the sub-lithographic dimension.
Vashishtha teaches that a gate extends past an active region by a sub-lithographic dimension (a vertical endcap of 4 nm past the active region, p. 51, 4.3 Standard Cell MOL Usage), wherein: the at least one end extends past the corresponding edge of the active region by the sub-lithographic dimension (the same 4 nm vertical endcap identified above).
As taught by Vashishtha, one of ordinary skill in the art would utilize and modify the above teaching into Chae to obtain and achieve that the gate extends past the active region by a sub-lithographic dimension, wherein: the at least one end extends past the corresponding edge of the active region by the sub-lithographic dimension as claimed, because sufficient separation is maintained to prevent reliability degradation such as time-dependent dielectric breakdown (TDDB) (p. 7, 2.1.4 Time-Dependent Dielectric Breakdown (TDDB)), and such separation is achieved by extending gate structure (e.g., through a gate cap and spacers) (p. 25, 3.1 Front End of Line (FEOL) and Middle of Line (MOL) Layers), while accounting for process variability such as edge placement error, which requires nanometer-scale margins (p. 26, 3.1 FEOL and MOL Layers), thereby resulting in a sub-lithographic dimension.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Vashishtha in combination with Chae due to the above reason.
Regarding claim 3, Chae in view of Vashishtha teaches the FET device according to claim 1, further comprising a spacer (Chae: the left spacer 119, Fig. 1B, [0059]) contacting the one end of the gate (the left end of 110).
Regarding claim 6, Chae in view of Vashishtha teaches the FET device according to claim 1, Chae does not teach the FET device wherein the sub-lithographic dimension is 5 nm or less along a longitudinal axis of the gate.
Vashishtha teaches that the sub-lithographic dimension is 5 nm or less along a longitudinal axis of the gate (a vertical endcap of 4 nm past the active region, p. 51, 4.3 Standard Cell MOL Usage).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Vashishtha to obtain and the FET device wherein the sub-lithographic dimension is 5 nm or less along a longitudinal axis of the gate as claimed, because it has been held that where the criticality of the claimed range is not shown and the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In reWertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP § 2144.05.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chae (US 2014/0353768) in view of Vashishtha (A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy, Arizona State University, 2019) as applied to claim 1 above, and further in view of Frougier et al. (US 2022/0231020; hereinafter ‘Frougier’).
Regarding claim 7, Chae in view of Vashishtha teaches the FET device according to claim 1, but does not teach the FET device wherein the gate comprises a replacement metal gate.
Frougier teaches a FET device (FIGS. 11A-11C, [0004]) wherein the gate comprises a replacement metal gate (the gate trenches and gaps enable formation of replacement metal gates, [0140]).
As taught by Frougier, one of ordinary skill in the art would utilize and modify the above teaching into Chae in view of Vashishtha to obtain and achieve the FET device wherein the gate comprises a replacement metal gate as claimed, because forming the replacement metal gate enables the gate to surround the nanosheet channels, thereby improving control of the channel region [0003, 0140].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Frougier in combination with Chae in view of Vashishtha due to the above reason.
Regarding claim 8, Chae in view of Vashishtha and Frougier teaches the FET device according to claim 7, but Chae in view of Vashishtha does not teach the FET device wherein the replacement metal gate comprises one of tungsten and aluminum.
Frougier teaches the FET device wherein the replacement metal gate comprises one of tungsten and aluminum (the gate electrode of the replacement metal gate is made of tungsten or aluminum, [0143]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Frougier to obtain and achieve the FET device wherein the replacement metal gate comprises one of tungsten and aluminum as claimed, because tungsten and aluminum are suitable conductive materials for forming gate electrodes in semiconductor devices. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chae (US 2014/0353768) in view of Vashishtha (A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy, Arizona State University, 2019) and Blatchford (US 2012/0331425).
Regarding claim 13, Chae teaches a field effect transistor (FET) device (Figs. 1A-1C, [0013]), comprising:
an active region (ACT, [0055]) comprising a source (124, [0059]) at a first end of the active region (the right end of ACT, Fig. 1C; hereinafter ‘ACTL2’) and a drain (122) at a second end of the active region (the left end of ACT; hereinafter ‘ACTL1’);
a gate (110, [0056]) extending transversely in a first direction across the active region (110 extending in D1 across ACT, Fig. 1A, [0056]) and comprising first (the end of 110 corresponding to L2; hereinafter ‘110L2’) and second (the end of 110 corresponding to L1; hereinafter ‘110L1’) opposite ends, the first end (110L2) extending past a first corresponding edge of the active region (ACTL2) and the second end (110L1) extending past a second corresponding edge of the active region (ACTL1), the gate having a rectangular shape with a uniform width from end-to-end in a second direction perpendicular to the first direction (110 having a rectangular shape with a uniform width Wg from end-to-end in D2, Fig. 1A, [0058, 0068]);
a contact (135, Fig. 1B, [0060]) having an annular shape that differs from the rectangular shape of the gate (135 having a circular shape, [0067]) and a diametric width which is less than the uniform width of the gate (the circular contact 135 having a diametric width Wc2 less than Wg of 110, Fig. 1A, [0068]); and
a spacer (the right spacer 119; hereinafter ‘119L2’) contacting the first ends of the gate (110L2).
Chae does not explicitly teach the FET device comprising: the contact being disposed in contact with the second end of the gate such that an entirety of the contact is disposed at an exterior of the active region.
Chae, however, provides that a gate contact 1236 contacting an end of a gate 1210 and being disposed entirely outside the footprint of active region ACT1 or ACT2 (Fig. 11, [0126])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Chae to obtain and achieve the FET device comprising: the contact being disposed in contact with the second end of the gate such that an entirety of the contact is disposed at an exterior of the active region as claimed, because positing the gate contact outside the active region prevents processing chemicals from penetrating through the gate material and deteriorating the underlying gate insulating layer, thereby protecting the gate dielectric and improving device reliability [0092].
Chae does not teach that the first gate end extends past the first edge of the active region by a sub-lithographic dimension and the second gate end extends past the second edge of the active region in excess of the sub-lithographic dimension.
Vashishtha teaches that the first gate end extends past the first edge of the active region by a sub-lithographic dimension (a vertical endcap of 4 nm past the active region, p. 51, 4.3 Standard Cell MOL Usage).
As taught by Vashishtha, one of ordinary skill in the art would utilize and modify the above teaching into Chae to obtain and achieve that the first gate end extends past the first edge of the active region by a sub-lithographic dimension as claimed, because sufficient separation is maintained to prevent reliability degradation such TDDB (p. 7, 2.1.4 TDDB), and such separation is achieved by extending gate structure (e.g., through a gate cap and spacers) (p. 25, 3.1 FEOL and MOL Layers), while accounting for process variability such as edge placement error, which requires nanometer-scale margins (p. 26, 3.1 FEOL and MOL Layers), thereby resulting in a sub-lithographic dimension.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Vashishtha in combination with Chae due to the above reason.
Chae in view of Vashishtha does not teach that the second gate end extends past the second edge of the active region in excess of the sub-lithographic dimension.
Blatchford teaches that the second gate end extends past the second edge of the active region in excess of the sub-lithographic dimension (a gate line end extends past an edge of an underlying active area, for example 25 nm, [0025]).
As taught by Blatchford, one of ordinary skill in the art would utilize and modify the above teaching into Chae in view of Vashishtha to obtain and achieve that the second gate end extends past the second edge of the active region in excess of the sub-lithographic dimension as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Blatchford in combination with Chae in view of Vashishtha due to the above reason.
Regarding claim 14, Chae in view of Vashishtha and Blatchford teaches the FET device according to claim 13, Chae in view of Blatchford does not teach the FET device wherein the sub-lithographic dimension is 5 nm or less along a longitudinal axis of the gate.
Vashishtha teaches that the sub-lithographic dimension is 5 nm or less along a longitudinal axis of the gate (a vertical endcap of 4 nm past the active region, p. 51, 4.3 Standard Cell MOL Usage).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Vashishtha to obtain and the FET device wherein the sub-lithographic dimension is 5 nm or less along a longitudinal axis of the gate as claimed, because it has been held that where the criticality of the claimed range is not shown and the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In reWertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP § 2144.05.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Chae (US 2014/0353768) in view of Vashishtha (A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy, Arizona State University, 2019) and Blatchford (US 2012/0331425) as applied to claim 13, and further in view of Frougier (US 2022/0231020).
Regarding claim 15, Chae in view of Vashishtha and Blatchford teaches the FET device according to claim 13, but does not teach the FET device wherein the gate comprises a replacement metal gate.
Frougier teaches a FET device (FIGS. 11A-11C, [0004]) wherein the gate comprises a replacement metal gate (the gate trenches and gaps enable formation of replacement metal gates, [0140]).
As taught by Frougier, one of ordinary skill in the art would utilize and modify the above teaching into Chae in view of Vashishtha and Blatchford to obtain and achieve the FET device wherein the gate comprises a replacement metal gate as claimed, because forming the replacement metal gate enables the gate to surround the nanosheet channels, thereby improving control of the channel region [0003, 0140].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Frougier in combination with Chae in view of Vashishtha and Blatchford due to the above reason.
Regarding claim 16, Chae in view of Vashishtha, Blatchford, and Frougier teaches the FET device according to claim 15, but Chae in view of Vashishtha and Blatchford does not teach the FET device wherein the replacement metal gate comprises one of tungsten and aluminum.
Frougier teaches the FET device wherein the replacement metal gate comprises one of tungsten and aluminum (the gate electrode of the replacement metal gate is made of tungsten or aluminum, [0143]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Frougier to obtain and achieve the FET device wherein the replacement metal gate comprises one of tungsten and aluminum as claimed, because tungsten and aluminum are suitable conductive materials for forming gate electrodes in semiconductor devices. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Vashishtha (A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy, Arizona State University, 2019) in view of Blatchford (US 2012/0331425), WEBB et al. (US 2016/0233298; hereinafter ‘WEBB’), and Chae (US 2014/0353768).
Regarding claim 17, Vashishtha teaches a field effect transistor (FET) device (Fig. 4.1, p. 45, 4.1 Gear Ratio and Cell Height), comprising:
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first (the upper-left active region; hereinafter ‘A1’), and second active regions (the lower-left active region; hereinafter ‘A2’), each comprising a source (an SD region formed in an active region adjacent to a first side of the gate, Fig. 3.1, corresponding to an active region adjacent to the gate in Fig. 4.1, p. 26, 3.1 Front End of Line (FEOL) and Middle of Line (MOL) Layers; hereinafter ‘S’) at a first end thereof (the left end of the active region) and a drain (an SD region formed in an active region adjacent to an opposite side of the gate; hereinafter ‘D’) at a second end thereof (the right end of the active region); and
first (the first gate disposed above the LIG feature that is second from a right side, p. 27, 3.1 Front End of Line (FEOL) and Middle of Line (MOL) Layers; hereinafter ‘G1’) and second gates (the second gate disposed below the LIG feature that is second from a right side; hereinafter ‘G2’) extending transversely across the first (A1) and second active regions (A2), respectively, each of the first (G1) and second gates (G2) comprising complementary first ends (the inner portion of G1 and G2; hereinafter ‘G1E1’ and ‘G2E1’) extending past first corresponding edges of the first (the edge of A1 adjacent to LIG; hereinafter ‘A1E1’) and second active regions (the edge of A2 adjacent to LIG; hereinafter ‘A2E1’) by a sub-lithographic dimension (a vertical endcap of 4 nm past the active region, p. 51, 4.3 Standard Cell MOL Usage) and complementary second ends (the inner portion of G1 and G2; hereinafter ‘G1E2’) extending past second corresponding edges of the first (the edge of A1 adjacent to the power rail; hereinafter ‘A1E2’) and second active regions (the edge of A2 adjacent to the power rail; hereinafter ‘A2E2’);
a contact (LIG) disposed in contact with the complementary first ends of the first (G1E1) and second gates (G2E1).
Vashishtha does not teach the FET device comprising: the second gate ends extend past second corresponding edges of the first and second active regions in excess of the sub-lithographic dimension; the contact disposed in contact with respective portions of the first and second gates defined between the complementary first ends of the first and second gates and the first corresponding edges of the first and second active regions, the contact overlapping with the respective portions of the first and second gates and the first corresponding edges of the first and second active regions; first spacers contacting the complementary first ends of the first and second gates; and second spacers contacting the complementary second ends of the first and second gates.
Blatchford teaches that the second gate ends extend past second corresponding edges of the first and second active regions in excess of the sub-lithographic dimension (a gate line end extends past an edge of an underlying active area, for example 25 nm, [0025]).
As taught by Blatchford, one of ordinary skill in the art would utilize and modify the above teaching into Vashishtha to obtain and achieve that the second gate end extends past the second edge of the active region in excess of the sub-lithographic dimension as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Blatchford in combination with Vashishtha due to the above reason.
Vashishtha in view of Blatchford does not teach the FET device comprising: the contact disposed in contact with respective portions of the first and second gates defined between the complementary first ends of the first and second gates and the first corresponding edges of the first and second active regions, the contact overlapping with the respective portions of the first and second gates and the first corresponding edges of the first and second active regions.
WEBB teaches a transistor device (FIG. 3D, [0026-0027]) comprising
a contact (local interconnect 340, [0027]) disposed in contact with respective portions of the first and second gates defined between the complementary first ends of the first and second gates and the first corresponding edges of the first and second active regions (340 contacting respective portions of first and second gates 320 and 322 located between their mutually facing ends adjacent to intervening isolation structure 314 and corresponding edges of semiconductor fins 302A and 302B, [0026-0027]),
the contact overlapping with the respective portions of the first and second gates (340 overlapping the respective portions of 320 and 322) and
the first corresponding edges of the first and second active regions (340 overlapping the corresponding edges of semiconductor fins 302A and 302B, which constitute respective non-planar active regions; [0026, 0056]).
As taught by WEBB, one of ordinary skill in the art would utilize and modify the above teaching into Vashishtha in view of Blatchford to obtain and achieve the FET device comprising: the contact disposed in contact with respective portions of the first and second gates defined between the complementary first ends of the first and second gates and the first corresponding edges of the first and second active regions, the contact overlapping with the respective portions of the first and second gates and the first corresponding edges of the first and second active regions as claimed, because a single local interconnect contacting both gates provides a direct conductive path between the gates over the intervening isolation structure, thereby simplifying the interconnection layout and improving device layout density [0018-0020, 0027].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by WEBB in combination with Vashishtha in view of Blatchford due to the above reason.
Vashishtha in view of Blatchford and WEBB does not teach the FET device comprising: first spacers contacting the complementary first ends of the first and second gates; and second spacers contacting the complementary second ends of the first and second gates.
Chae teaches a FET device (Figs. 8A and 8B, [0013]) comprising: first spacers (the right spacer 319 of 310d and the left spacer 319 of 310b, [0155]) contacting the complementary first ends of the first (the side of 310d adjacent to Va, [0161]) and second gates (the side of 310b adjacent to Va); and second spacers (the left spacer 319 of 310d and the right spacer 319 of 310b) contacting the complementary second ends of the first (the side of 310d opposite Va) and second gates (the side of 310b opposite Va).
As taught by Chae, one of ordinary skill in the art would utilize and modify the above teaching into Vashishtha in view of Blatchford and WEBB to obtain and achieve the FET device comprising: first spacers contacting the complementary first ends of the first and second gates; and second spacers contacting the complementary second ends of the first and second gates as claimed, because spacers are conventionally provided o sidewalls of gate electrodes to electrically isolate the gate and to enable self-aligned formation of source/drain regions [0059].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Chae in combination with Vashishtha in view of Blatchford and WEBB due to the above reason.
Regarding claim 18, Vashishtha in view of Blatchford, WEBB, and Chae teaches the FET device according to claim 17, wherein the sub-lithographic dimension is 5 nm or less along a longitudinal axis of each of the first and second (Vashishtha: a vertical endcap of 4 nm past the active region, p. 51, 4.3 Standard Cell MOL Usage).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Vashishtha (A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy, Arizona State University, 2019) in view of Blatchford (US 2012/0331425), WEBB (US 2016/0233298), and Chae (US 2014/0353768) as applied to claim 17, and further in view of Frougier (US 2022/0231020).
Regarding claim 19, Vashishtha in view of Blatchford, WEBB, and Chae teaches the FET device according to claim 17, but does not teach the FET device wherein the first and second gates each comprises a replacement metal gate.
Frougier teaches a FET device (FIGS. 11A-11C, [0004]) wherein the gate comprises a replacement metal gate (the gate trenches and gaps enable formation of replacement metal gates, [0140]).
As taught by Frougier, one of ordinary skill in the art would utilize and modify the above teaching into Vashishtha in view of Blatchford, WEBB, and Chae to obtain and achieve the FET device wherein the first and second gates each comprises a replacement metal gate as claimed, because forming the replacement metal gate enables the gate to surround the nanosheet channels, thereby improving control of the channel region [0003, 0140].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Frougier in combination with Vashishtha in view of Blatchford, WEBB, and Chae due to the above reason.
Regarding claim 20, Vashishtha in view of Blatchford, WEBB, Chae, and Frougier teaches the FET device according to claim 19, but Vashishtha in view of Blatchford, WEBB, and Chae does not teach the FET device wherein the replacement metal gate comprises one of tungsten and aluminum.
Frougier teaches the FET device wherein the replacement metal gate comprises one of tungsten and aluminum (the gate electrode of the replacement metal gate is made of tungsten or aluminum, [0143]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Frougier to obtain and achieve the FET device wherein the replacement metal gate comprises one of tungsten and aluminum as claimed, because tungsten and aluminum are suitable conductive materials for forming gate electrodes in semiconductor devices. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Claims 1 and 13
Applicant submits, in page 9 of Remark, that
“The combination of features noted above is missing from any proper combination of the cited references”.
The examiner respectfully disagrees.
An obviousness determination does not require that all claimed features be expressly depicted together in a single embodiment of Chae. Chae expressly discloses: (i) a gate contact plug having a circular shape in plan view [0067]; (ii) a substantially uniform gate width greater than the width of the gate contact plug [0068]; (iii) gate contact plugs disposed entirely outside the respective footprints of active regions ACT1 and ACT2 (FIG. 11, [0126]). The contact’s plan view shape and width concern the contact’s physical configuration, whereas its position relative to the active region footprint concerns its placement. Applicant has not identified any technical incompatibility or any teaching in Chae that would discourage the combined use of these disclosed features. Accordingly, combining these expressly disclosed features would have been a predictable use of Chae’s disclosed alternative according to their established functions.
Applicant submits, in page 10 of Remark, that
“all of Chae’s contacts are squared or rectangular”.
The examiner respectfully disagrees.
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Paragraph [0067] of Chae expressly teaches that the gate contact plug may have a circular shape in plan view. Under Applicant’s interpretation shown in its annotated FIG. 2, the claimed “annular shape” encompasses the illustrated circular plan-view shape of contact 230. Accordingly, Chae’s circular contact corresponds to the claimed annular shape, and no unsupported modification of Chae is required.
Applicant submits, in page 10 of Remark, that
“, would mean reducing the contact interface between Chae’s contacts and gates”.
The examiner respectfully disagrees.
Any reduction in contact-interface area is a predictable geometric consequence of using Chae’s disclosed smaller circular contact. Paragraph [0068] expressly teaches that the substantially uniform gate width may be greater than the contact plug width, including approximately 110% to 130% of the contact width, thereby providing an alignment margin. Application has not shown that the smaller interface would render Chae inoperative or produce an unexpected result.
Conclusion
Applicant's amendment necessitated the new ground of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 9/14/26
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