DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Note by the Examiner For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 &/or 103 rejections are provided in parenthesis. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim s FILLIN "Enter claim indentification information" \* MERGEFORMAT 2 -7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim FILLIN "Enter claim identification information" \* MERGEFORMAT 2 recites the limitation " FILLIN "Enter appropriate information" \* MERGEFORMAT The semiconductor device " in FILLIN "Enter appropriate information" \* MERGEFORMAT the beginning of the claim . There is insufficient antecedent basis for this limitation in the claim and the claim it depends on . Applicant should also note that C laims 3-7 also recite “The semiconductor device” at their start, which may cause further issues if not addressed properly . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application , as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. center 672244 0 0 Claim 1 is rejected under 35 U.S.C. 102 FILLIN "Insert either \“(a)(1)\” or \“(a)(2)\” or both. If paragraph (a)(2) of 35 U.S.C. 102 is applicable, use form paragraph 7.15.01.aia, 7.15.02.aia or 7.15.03.aia where applicable." \d "[ 2 ]" (a)(1) as being FILLIN "Insert either—clearly anticipated—or—anticipated—with an explanation at the end of the paragraph." \d "[ 3 ]" anticipated by FILLIN "Insert the prior art relied upon." \d "[ 4 ]" Lee et al. (Pub. No.: US 2023/0200054 A1), hereinafter as Lee . Image A : a close up of Lee’s Fig. 4 V . With regards to Claim 1 , Lee discloses a cutting structure (see above Image A and Lee Fig. 4 V ) , comprising: two primary cutting insulating layers (Lee Fig. 4 V , outer insulating spacers 148) positioned on two ends of a secondary cutting insulating layer (Lee Fig. 4 V , buffer layer 122) and extending upwardly (Lee Fig. 4 V and Image A) , wherein the two primary cutting insulating layers and the secondary cutting insulating layer together configure a U-shaped cross-sectional profile (Lee Fig. 4 V and Image A) ; a conductive portion (Lee Fig. 4 V , bit line BL (130, 132, 134 ) positioned on the secondary cutting insulating layer and laterally surrounded by the two primary cutting insulating layers (Lee Fig. 4 V and Image A) ; and a capping portion (Lee Fig. 4 V , insulating capping pattern 136) positioned on the conductive portion and laterally surrounded by the two primary cutting insulating layers (Lee Fig. 4 V and Image A) . Claims FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 1, 2, and 4 are rejected under 35 U.S.C. 102 FILLIN "Insert either \“(a)(1)\” or \“(a)(2)\” or both. If paragraph (a)(2) of 35 U.S.C. 102 is applicable, use form paragraph 7.15.01.aia, 7.15.02.aia or 7.15.03.aia where applicable." \d "[ 2 ]" (a)(1) as being FILLIN "Insert either—clearly anticipated—or—anticipated—with an explanation at the end of the paragraph." \d "[ 3 ]" anticipated by FILLIN "Insert the prior art relied upon." \d "[ 4 ]" Tung et al. (Pub. No.: US 2023/0335491 A1), hereinafter as Tung . With regards to Claim 1 , Tung discloses a cutting structure, comprising (Tung Fig. 9, passing gates PG) : two primary cutting insulating layers (Tung Fig. 4-6 and 8-9, first dielectric layer 20 (which later on is named the isolation structure 20a)) positioned on two ends of a secondary cutting insulating layer (Tung Fig. 9, second dielectric layer 30) and extending upwardly (Tung Fig. 9) , wherein the two primary cutting insulating layers and the secondary cutting insulating layer together configure a U-shaped cross-sectional profile (Tung Fig. 9) ; a conductive portion (Tung Fig. 9, conductive layer 44) positioned on the secondary cutting insulating layer and laterally surrounded by the two primary cutting insulating layers (Tung Fig. 9 , isolation structure 20a ) ; and a capping portion (Tung Fig. 9, capping layer 46) positioned on the conductive portion and laterally surrounded by the two primary cutting insulating layers (Tung Fig. 9) . With regards to Claim 2 , Tung discloses the semiconductor device of claim 1, wherein top surfaces of the two primary cutting insulating layers (Tung Fig. 9 , isolation structure 20a ) and the capping portion (Tung Fig. 9, capping layer 46) are substantially coplanar (Tung Fig. 9) . With regards to Claim 4 , Tung discloses the semiconductor device of claim 2, wherein bottom surfaces of the two primary cutting insulating layers (Tung Fig. 4-6 and 8-9, first dielectric layer 20 (which later on is named the isolation structure 20a)) and the secondary cutting insulating layer (Tung Fig. 9, second dielectric layer 30) are at different vertical levels (Tung Fig. 9) . center 699742 0 0 Claims FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 8 and 13 are rejected under 35 U.S.C. 102(a)(2) as being FILLIN "Insert either --clearly anticipated-- or--anticipated-- with an explanation at the end of the paragraph." \d "[ 2 ]" anticipated by FILLIN "Insert the prior art relied upon" \d "[ 3 ]" Luo et al. (Patent No.: 11,871,555 B2), hereinafter as Luo , using Luo’s filing date . Image B: a close up of Luo’s Fig. 2 N With regards to Claim 8 , Luo discloses a semiconductor device (semiconductor structure, see Luo’s Abstract) , comprising: an isolation layer (Luo Fig. 2A -2N, shallow trench isolation areas 202) positioned in a substrate (“The semiconductor substrate has multiple separate active areas 201 that are isolated from each other by shallow trench isolation areas 202.” (Luo col. 3, ln. 25-27)) to define a pre-cutting area (Luo Fig. 2A, active areas 201) along a first tilt direction in a top-view perspective (Luo Fig. 2A) ; at least two cutting structures (Luo Fig. 2H, first trench 203A) positioned in the pre-cutting area and respectively comprising (Luo Fig. 2H and 2N) : two primary cutting insulating layers (side portions of a dielectric layer 240 as seen in above Image B and Luo Fig. 2K) positioned on two ends of a secondary cutting insulating layer (bottom portion of the dielectric layer 240 as seen in Image B and Luo Fig. 2K) and extending upwardly (Luo Fig. 2N) , wherein the two primary cutting insulating layers and the secondary cutting insulating layer together configure a U-shaped cross-sectional profile (Luo Fig. 2N) ; a conductive portion (Luo Fig. 2K, conductive layer 260) positioned on the secondary cutting insulating layer and laterally surrounded by the two primary cutting insulating layers (Luo Fig. 2K and 2N) ; and a capping portion (Luo Fig. 2N, protective layer 280) positioned on the conductive portion and laterally surrounded by the two primary cutting insulating layers (Luo Fig. 2N) ; wherein an active area (Luo Fig. 2A-2N, active areas 201) is defined within the pre-cutting area by an adjacent pair of the cutting structures (Luo Fig. 2N) . With regards to Claim 13 , Luo discloses the semiconductor device of claim 8, wherein the two primary cutting insulating layers and the secondary cutting insulating layer comprise the same material (the side portions and the bottom portion are made of the same material because they make up the same dielectric layer 240, as seen in Image B and Fig. 2K . For the material, see Luo col. 6, ln. 10-11: “The dielectric layer 240 may be an oxide layer, which may serve as a gate oxide layer.” ) . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . Claims FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 2, 3, and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Tung. With regards to Claim 2 , Lee discloses the semiconductor device of claim 1. Lee does not disclose that top surfaces of the two primary cutting insulating layers and the capping portion are substantially coplanar. Tung discloses the semiconductor device of claim 1, wherein top surfaces of the two primary cutting insulating layers (Tung Fig. 9, isolation structure 20a) and the capping portion (Tung Fig. 9, capping layer 46) are substantially coplanar (Tung Fig. 9) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device of Lee with the coplanarity of the top surfaces of the two primary cutting insulating layers, the capping portion, and the substrate taught by Tung in order to make the device’s surface flat to allow formation of additional circuit elements. With regards to Claim 3 , Lee (in combination with Tung) discloses the semiconductor device of claim 2, wherein bottom surfaces of the two primary cutting insulating layers and the secondary cutting insulating layer are substantially coplanar (Lee Fig. 4V and Image A) . With regards to Claim 5 , Lee (in combination with Tung) discloses the semiconductor device of claim 2, wherein the conductive portion comprises a bottom segment (Lee Fig. 4V, lower conductive layer 130) and a top segment (Lee Fig. 4V, upper conductive layer 134) , the bottom segment is positioned on the secondary cutting insulating layer (Lee Fig. 4V, buffer layer 122) and is laterally surrounded by the two primary cutting insulating layers (Lee Fig. 4V and Image A) , and the top segment is positioned between the bottom segment and the capping portion and is laterally surrounded by the two primary cutting insulating layers (Lee Fig. 4V and Image A) . With regards to Claim 6 , Lee (in combination with Tung) discloses the semiconductor device of claim 5, wherein the two primary cutting insulating layer and the secondary cutting insulating layer comprise the same material (“In example embodiments, the outer insulating spacer 148 may include or may be a SiN layer” (see Lee [0033]), and “The buffer layer 122 may include or may be formed of a first silicon oxide layer, a silicon nitride ( SiN ) layer, and a second silicon oxide layer” (see Lee [0023]), shows that the insulating layers can comprise of the same material. In this case, both insulating layers have a SiN layer) . With regards to Claim 7 , Lee (in combination with Tung) discloses the semiconductor device of claim 5, wherein the two primary cutting insulating layer and the secondary cutting insulating layer comprise different materials ( “In example embodiments, the outer insulating spacer 148 may include or may be a SiN layer” (see Lee [0033]), and “The buffer layer 122 may include or may be formed of a first silicon oxide layer, a silicon nitride ( SiN ) layer, and a second silicon oxide layer” (see Lee [0023]), showing that the insulating layers can comprise of different materials) . center 991677 Claims FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 9, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art relied upon." \d "[ 2 ]" Luo (using Luo’s filing date) in view of Kim et al. (Pub. No.: US 20220399456 A1), hereinafter as Kim . Image C: a close up of Kim’s Fig. 4 With regards to Claim 9 , Luo discloses the semiconductor device of claim 8 . Luo does not disclose top surfaces of the two primary cutting insulating layers, the capping portion, and the substrate are substantially coplanar. However, Kim discloses top surfaces of the two primary cutting insulating layers (side portions of a gate insulating layer 203 as seen in Image C and Kim Fig. 4 ) , the capping portion (Kim Fig. 4 , capping layer 205) , and the substrate (Kim Fig. 4 , substrate 201 , first doped region 206, and second doped region 207 ) are substantially coplanar (Kim Fig. 4 ) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device of Luo with the coplanarity of the top surfaces of the two primary cutting insulating layers , the capping portion, and the substrate taught by Kim in order to make the device’s surface flat to allow formation of additional circuit elements. With regards to Claim 10 , Luo discloses the semiconductor device of claim 8. Luo does not disclose bottom surfaces of the two primary cutting insulating layers and the secondary cutting insulating layer are substantially coplanar. However, Kim discloses bottom surfaces of the two primary cutting insulating layers (side portions of the gate insulating layer 203 as seen in Image C and Kim Fig. 4 ) and the secondary cutting insulating layer (bottom portion of the gate insulating layer 203 as seen in Image C and Kim Fig. 4 ) are substantially coplanar (Kim Fig. 4 ) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device of Luo with the coplanarity of the bottom surfaces of the two primary cutting insulating layers and the secondary cutting insulating layer taught by Kim in order to conformally form the insulating layers inside trench-like spaces. With regards to Claim 12 , Luo discloses the semiconductor device of claim 8. Luo does not disclose that the conductive portion comprises a bottom segment and a top segment, the bottom segment is positioned on the secondary cutting insulating layer and is laterally surrounded by the two primary cutting insulating layers, and the top segment is positioned between the bottom segment and the capping portion and is laterally surrounded by the two primary cutting insulating layers. However, Kim discloses a conductive portion (Kim Fig. 4 , buried word line BWL ( 204 ) ) comprises a bottom segment (Kim Fig. 4 , lower conductive layer 204L ) and a top segment (Kim Fig. 4 , upper conductive layer 204U ) , the bottom segment is positioned on the secondary cutting insulating layer (bottom portion of the gate insulating layer 203 as seen in Image C and Kim Fig. 4 ) and is laterally surrounded by the two primary cutting insulating layers (side portion of the gate insulating layer 203 as seen in Image C and Kim Fig. 4 ) , and the top segment is positioned between the bottom segment and the capping portion (Kim Fig. 4 , capping layer 205) and is laterally surrounded by the two primary cutting insulating layers (side portion of the gate insulating layer 203 as seen in Image C and Kim Fig. 4 ) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the conductive portion of Luo with the conductive portion taught by Kim in order to improve gate-induced drain leakage (see Kim [0062]: “Gate-induced drain leakage (GIDL) may be improved by the low work function of the upper conductive layer 204U.”). center 903135 Claims FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 11 and 14 -18 are rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art relied upon." \d "[ 2 ]" Luo in view of Tung . Image D: a close up of Tung’s Fig. 9 With r egards to Claim 11 , Luo discloses the semiconductor device of claim 8. Luo does not disclose bottom surfaces of the two primary cutting insulating layers and the secondary cutting insulating layer are at different vertical levels. However, Tung discloses bottom surfaces of the two primary cutting insulating layers (Tung Figs. 4-6 and 8-9, first dielectric layer 20 (which later on is named the isolation structure 20a)) and the secondary cutting insulating layer (Tung Fig. 9, second dielectric layer 30 (30a) ) are at different vertical levels (Tung Fig. 9) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device of Luo with the different vertical levels taught by Tung in order to improve electrical isolation between adjacent memory cells (see Tung [0018]: “The dielectric insert structures 30a are deeper than the isolation structure 20a and may improve electrical isolation between adjacent memory cells , so that signal crosstalk between the memory cells may be reduced.”) With regards to Claim 14 , Luo discloses the semiconductor device of claim 8. Luo does not disclose that the two primary cutting insulating layers and the secondary cutting insulating layer comprise different materials. However, Tung discloses that the two primary cutting insulating layers (Tung Figs. 4-6 and 8-9, first dielectric layer 20(20a)) and the secondary cutting insulating layer (Tung Fig. 9, second dielectric layer 30 (30a) ) comprise different materials ("the first dielectric layer 20 is made of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof,” (see Tung [0013]) and that "the second dielectric layer 30 is made of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof,” (see Tung [0015]), showing that the first and second dielectric layers can be made of different materials from each other) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the material of the cutting insulating layers of Luo with the differing materials taught by Tung in order to create a depletion region and further obstruct leakage currents between memory cells (see Tung [0015] , [0016], and [0018]: “In an embodiment, the first dielectric layer 20 is made of silicon oxide, and the second dielectric layer 30 is made of silicon nitride. The second dielectric layer 30 may be used as a solid-state doping (SSD) source layer, and may include neutral dopants (such as carbon) or dopants of a specific conductivity type. In some embodiments, the second dielectric layer 30 may include dopants of a second conductivity type opposite to the first conductivity type of the well region.”; “ In some embodiments when the dielectric insert structures 30a includes dopants and is used as a solid state doping (SSD) source layer, an anneal process may be performed to drive the dopants from the dielectric insert structures 30a into the substrate 10 after forming the word line trenches 40 to form the doped regions 30b in the substrate 10 and directly under the isolation trench 14. ”; “Furthermore, by forming a doped regions 30b with a conductivity type opposite to the conductivity type of the substrate 10 (or the well region), a depletion region may be formed to obstruct leakage currents between memory cells .” ; in order to create the depletion region 30b , the secondary cutting insulating layer (Tung Fig. 9, second dielectric layer 30 (30a) ) must be doped , which means the primary and secondary cutting insulators are made of different materials. ). With regards to Claim 15 , Luo disclose s the semiconductor device of claim 8, further comprising a first word line structure (Luo Fig. 2N, first word line 270A) in the active area (Luo Fig. 2N, active areas 201) . With regards to Claim 16 , Luo disclose s the semiconductor device of claim 15, wherein the first word line structure comprises: a first word line dielectric layer (Luo Fig. 2K, dielectric layer 240) positioned in the active area and comprises a U-shaped cross-sectional profile (Luo Fig. 2K) ; a first word line conductive layer (Luo Fig. 2K, conductive layer 260) positioned on the first word line dielectric layer (Luo Fig. 2K) ; and a first word line capping layer (Luo Fig. 2N, protective layer 280) positioned on the first WL conductive layer (Luo Fig. 2N) . With regards to Claim 17 , Luo discloses the semiconductor device of claim 16 . Luo does not disclose a bottom surface of the first word line dielectric layer is at a vertical level higher than a bottom surface of the secondary cutting insulating layer. Tung discloses a bottom surface of the first word line dielectric layer (Tung Fig. 9 , gate dielectric layer 42) is at a vertical level higher than a bottom surface of the secondary cutting insulating layer (Tung Fig. 9 and above Image D) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the word line of Luo with the different vertical levels described by Tung in order to further obstruct leakage currents between memory cells (see Tung [0016] and [0018] : “ In some embodiments when the dielectric insert structures 30a includes dopants and is used as a solid state doping (SSD) source layer, an anneal process may be performed to drive the dopants from the dielectric insert structures 30a into the substrate 10 after forming the word line trenches 40 to form the doped regions 30b in the substrate 10 and directly under the isolation trench 14. ”; “Furthermore, by forming a doped regions 30b with a conductivity type opposite to the conductivity type of the substrate 10 (or the well region), a depletion region may be formed to obstruct leakage currents between memory cells.” ; the doped secondary cutting insulating layer (Tung Fig. 9, second dielectric layer 30 (30a) ) extends further into the substrate 1 0 than the bottom of the word line WL and creates the depletion region 30b , which is necessary to further obstruct leakage currents.). With regards to Claim 18 , Tung (in combination with Luo) discloses the semiconductor device of claim 17, wherein the first word line dielectric layer (Tung Fig. 9 , gate dielectric layer 42) and the secondary cutting insulating layer (Tung Fig. 9, second dielectric layer 30 (30a) ) comprise the same material ("the material of the gate dielectric layer 42 may include silicon oxide, silicon nitride, high-k dielectric materials, or a combination thereof, but is not limited thereto,” (see Tung [0017]) and that "the second dielectric layer 30 is made of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof,” (see Tung [0015]), showing that the gate dielectric layer 42 and the second dielectric layer 30 can comprise of the same material) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT EKATERINA T BIRCH whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-8676 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Mon- Fri , 8am- 4 pm ET . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Steven Loke can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 5712721657 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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