DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Election/Restrictions Applicant's election with traverse of Species I directed to Fig. 4-5 (claims 1-4, 8-9 and 13-16 ) in the reply filed on March 6 th , 20 26 is acknowledged. The traversal is on the ground(s) that the office fails to provide any facts to show serious burden in examining all pending claims and species . This is not found persuasive because the office is not require d to provide any facts for showing serious burden but rather than providing two requirements for the restriction on species: 1) the office provided rationales that all disclosed species are distinct (see pg. 2 of the restriction) , and 2) the office provided reasons why examining all species are serious burden. The requirement is still deemed proper and is therefore made FINAL. Claims 5-7 and 10-12 and 17-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application , as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2 , 4 , 8-9 and 13-15 are rejected under 35 U.S.C. 102(a)( 2 ) as being anticipated by Kim et al. (Pub. No.: US 20 22/0310676 A1), hereinafter as Kim . Regarding claim 1 , Kim discloses a n image sensing device in Figs. 1-2 comprising: a semiconductor substrate (substrate 101) including a first surface (surface 100b) and a second surface (surface 100a) facing or opposite to the first surface, and structured to include a pixel region (pixel region PR of central region CR) in which photoelectric conversion elements (region PDs) are formed to correspond to unit pixels (unit pixels of regions PR) and a pad region (region having contact pattern CT and contact plug PLG) that is located outside the pixel region while having an electrode pad (contact pattern CT) (see Fig. 2 and [0027-0029], [0047]) ; a pixel isolation pattern ( a isolation structure PIS2 in pixel region PR) disposed between the photoelectric conversion elements in the semiconductor substrate (see Fig. 2 and [0026]) ; and a pad isolation pattern (a combination of isolation structure s PIS1 , PIS2 and isolation layer 105 in region DPR as shown in annotated Fig. 2) disposed between the pixel region and the pad region in the semiconductor substrate, wherein the pad isolation pattern includes: at least one first upper isolation pattern (isolation structure PIS2 in the illustrated pad isolation pattern in the region DPR) formed to extend from the first surface toward the second surface to have a same depth (same depth with PIS2 in the region PR) as the pixel isolation pattern (see Fig. 2 and [0028], [0031-0032]) ; and at least one second upper isolation pattern (isolation structure PIS1 in the illustrated pad isolation pattern in the region DPR) formed to extend from a bottom surface of the at least one first upper isolation pattern (bottom surface of dielectric layer 121) toward the second surface, wherein an upper surface of the at least one second upper isolation pattern has a smaller width (a width of upper surface of liner insulating pattern 111 of PIS1) than the bottom surface of the at least one first upper isolation pattern (width of bottom surface of dielectric layer 121) (see illustrated pad isolation pattern in annotated Fig. 2 above and [0036], [0059]) . Regarding claim 2 , Kim discloses t he image sensing device according to claim 1, wherein the pad isolation pattern further includes: a lower isolation pattern (isolation layer 105) formed to extend from the second surface of the semiconductor substrate toward the first surface of the semiconductor substrate, wherein a bottom surface of the lower isolation pattern (bottom surface of isolation layer 105) is connected to the at least one second upper isolation pattern (isolation structure PIS1) (see Fig. 2 and [0029]) . Regarding claim 4 , Kim discloses t he image sensing device according to claim 2, wherein: the pad isolation pattern is formed to penetrate the semiconductor substrate (the combination of isolation structures PIS1, PIS2 and isolation layer 105 in region DPR penetrate substrate 101 as shown in annotated Fig. 2). Regarding claim 8 , Kim discloses t he image sensing device according to claim 1, wherein: the pad isolation pattern is formed in a loop shape surrounding the pixel region (see Fig. 1 and 2) . Regarding claim 9 , Kim discloses t he image sensing device according to claim 1 , wherein: the first and second upper isolation patterns are configured to include a same insulation material as the pixel isolation pattern (dielectric layer 121 includes hafnium oxide and liner insulation pattern 111 includes hafnium oxide) (see Fig. 2 and [0037] and [0059]) . Regarding claim 1 3 , Kim discloses an image sensing device in Figs. 1-2 comprising: a semiconductor substrate (substrate 101) structured to include a pixel region (pixel region PR of central region CR) in which photoelectric conversion elements (region PDs) for photoelectric conversion of incident light are formed and a pad region (region having contact pattern CT and contact plug PLG) that is located outside the pixel region while having an electrode pad (contact pattern CT) (see Fig. 2 and [0027-0029], [0047]) ; a pixel isolation pattern (a n isolation structure PIS2 in pixel region PR) vertically extending to a first depth in the semiconductor substrate (a dept of which isolation structure PIS2 extend to in pixel region PR) and disposed between the photoelectric conversion elements (see Fig. 2 and [0026]) ; and a pad isolation pattern (a combination of isolation structures PIS1, PIS2 and isolation layer 105 in region DPR as shown in annotated Fig. 2 above ) vertically extending in the semiconductor substrate to a second depth (equal to the depth of surface 100a where isolation layer 105 extends to) greater than the first depth and disposed between the pixel region and the pad region, wherein the pad isolation pattern has a stepped shape at the first depth (stepped shape formed at the region meeting between bottom surface of dielectric layer 121 and top surface of liner insulating pattern 111) (see illustrated pad isolation pattern in annotated Fig. 2 above and [0028], [0031-0032], [0036], [0059]) . Regarding claim 14 , Kim discloses t he image sensing device according to claim 13 , wherein the pad isolation pattern includes: at least one first upper isolation pattern (isolation structure PIS2 in the illustrated pad isolation pattern in the region DPR) formed to extend to the first depth in the semiconductor substrate from a first surface of the semiconductor substrate ( surface 100b ) (see Fig. 2 and [0028], [0031-0032]); and at least one second upper isolation pattern (isolation structure PIS1 in the illustrated pad isolation pattern in the region DPR) formed to extend from a bottom surface of the at least one first upper isolation pattern (bottom surface of dielectric layer 121) toward the second surface, wherein an upper surface of the at least one second upper isolation pattern has a smaller width (a width of upper surface of liner insulating pattern 111 of PIS1) than the bottom surface of the at least one first upper isolation pattern (width of bottom surface of dielectric layer 121) (see illustrated pad isolation pattern in annotated Fig. 2 above and [0036], [0059]). Regarding claim 15 , Kim discloses t he image sensing device according to claim 1 4 , wherein the pad isolation pattern further includes: a lower isolation pattern (isolation layer 105) formed to extend from a second surface of the semiconductor substrate (surface 100a) toward the first surface of the semiconductor substrate (surface 100b) , wherein the second surface is opposite to the first surface, wherein a bottom surface of the lower isolation pattern (bottom surface of isolation layer 105) is connected to the at least one second upper isolation pattern (isolation structure PIS1) (see Fig. 2 and [0029]) . Allowable Subject Matter Claims 3 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner's statement of reasons for the indication of allowable subject matter: wherein: the lower isolation pattern of the pad isolation pattern is connected to two or more of the at least one second upper isolation pattern as recited in claim s 3 and 16 . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT CUONG B NGUYEN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1509 (Email: CuongB.Nguyen@uspto.gov) . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Steven H. Loke can be reached on FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-1657 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CUONG B NGUYEN/ Primary Examiner, Art Unit 2818