Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18508638 filed on 11/14/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
Applicant’s election claims 1-14 the reply filed on 5/22/2026 is acknowledged.
Allowable subject matter
Claims 2-9 are objected to as being dependent upon a rejected base claim (independent claim 18), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Wu et al. (CN 114975467 A).
With respect to dependent claims 2-9, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein: each row of the support pillar structures extends along the first horizontal direction with a uniform pitch; and the variable width of the lateral isolation trench fill structure has a periodic undulation along the first horizontal direction with a periodicity that is the same as the uniform pitch”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (CN 114975467 A) in view of Zhou et al. (US 2024/0349500).
Regarding Independent claim 1, Wu et al. teach a three-dimensional memory device, comprising:
a pair of alternating stacks, wherein each alternating stack within the pair of alternating stacks comprises insulating layers (Fig. 2, specification discloses stack structure 120 comprising interlayer insulating film) and electrically conductive layers (Fig. 2, specification discloses stack structure 120 comprising gate layers) that are interlaced along a vertical direction, and
wherein the pair of alternating stacks are laterally spaced from each other by a lateral isolation trench (Fig. 2, element 11) that laterally extends along a first horizontal direction;
memory openings (Fig. 2, element 21) vertically extending through a respective one of the pair of alternating stacks;
memory opening fill structures located in a respective one of the memory openings and comprising a respective vertical semiconductor channel (Fig. 2, element 23) and a respective vertical stack of memory elements (Fig. 2, elements 22 & 24);
a lateral isolation trench fill structure (Fig.4, elements 111a & 112a) having a variable width along a second horizontal direction and located in the lateral isolation trench, the lateral isolation trench fill structure comprising:
a plurality of neck portions (Fig. 4, element 111a) having a pair of straight sidewalls which extend along the first horizontal direction and having a first width along the second horizontal direction that is perpendicular to the first horizontal direction; and
a plurality of laterally bulging portions (Fig. 4, element 112a) having a second width along the second horizontal direction that is greater than the first width, wherein the plurality of laterally bulging portions is interlaced with the plurality of neck portions along the first horizontal direction.
Wu et al. teach do not explicitly disclose rows of support pillar structures, wherein each row of the support pillar structures laterally extends along the first horizontal direction and vertically extends through a respective one of the pair of alternating stacks.
Zhou et al. teach a memory device comprising layer comprising disclose rows of support pillar structures (Fig. 12, element 20, paragraph 0077), wherein each row of the support pillar structures laterally extends along the first horizontal direction and vertically extends through a respective one of the pair of alternating stacks (Fig. 12, stack of elements 46 & 32, paragraph 0098).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Wu et al. according to the teachings of Zhou et al. with the motivation to provide structural support to the insulating layers 32 and the stepped dielectric material portion 65 during replacement of the sacrificial material layers 42 with electrically conductive layers (paragraph 0077).
Regarding claim 10, Wu et al. modified by Zhou et a. teach a contact-level dielectric layer (Fig. 12, element 80, paragraph 0089 of Zhou) overlying the pair of alternating stacks and comprising two portions that are laterally spaced apart by the lateral isolation trench (Fig. 12, element 79 of Zhou); and drain contact via structures (Fig. 12, element 88, paragraph 0102 of Zhou) vertically extending through the contact-level dielectric layer and contacting a top surface of a respective one of the memory opening fill structures, wherein all top surfaces of the support pillar structures are in contact with a bottom surface of the contact-level dielectric layer (Fig. 12 of Zhou).
Regarding claim 11, Wu et al. modified by Zhou et al. teach wherein the support pillar structures contain only dielectric material or dielectric materials (paragraph 0077 of Zhou discloses silicon oxide).
Regarding claim 12, Wu et al. modified by Zhou et al. teach wherein the rows of support pillar structures are arranged as two rectangular arrays of support pillar structures located within a respective alternating stack of the pair of alternating stacks (Figs. 11B & 12 of Zhou).
Regarding claim 13, Wu et al. modified by Zhou et al. teach wherein: each alternating stack of the pair of alternating stacks comprises a respective staircase region (Fig. 12 of Zhou) in which lateral extents of electrically conductive layers within said each alternating stack along the first horizontal direction vary with a vertical distance from a horizontal plane including bottommost surfaces of the pair of alternating stacks (Fig. 12 of Zhou); and the rows of support pillar structures are located in the staircase regions of the pair of alternating stacks (Fig. 12 of Zhou).
Regarding claim 14, Wu et al. modified by Zhou et al. teach wherein the lateral isolation trench fill structure has a uniform width throughout within a region that is located between a first subset of the memory opening fill structures vertically extending through a first alternating stack within the pair of alternating stacks and a second subset of the memory opening fill structures vertically extending through a second alternating stack within the pair of alternating stacks (Fig. 4 of Wu).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHAHED AHMED/
Primary Examiner, Art Unit 2813
Prosecution Insights