DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-10 in the reply filed on 2/25/2026 is acknowledged.
Invention II, claims 11-17 are withdrawn.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application KR 10-2023-0020741 filed in Korean Intellectual Property Office (KIPO) on 2/16/2023 and receipt of a certified copy thereof.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 8/1/2024 and IDS filed on 7-29/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDSs are considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 6 is objected to because of the following informalities:
In claim 6, line 7, “the JFET being disposed” should read --the JFET region being disposed-- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 9 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tarui (US 2012/0112266).
Regarding claim 9, Tarui teaches a power semiconductor device (FIG. 18, [0085]), comprising:
a semiconductor layer (2, [0087]) comprising silicon carbide (SiC) (SiC, [0057, 0060]), the semiconductor layer (2) including a protrusion (protrusion of 2, [0091]; hereinafter ‘2P’) formed upwards from a partial portion of an upper region of the semiconductor layer (shown in FIG. 18);
a gate insulation layer (6, [0086]) disposed on the semiconductor layer (2) disposed to cover the protrusion (2P), and comprising a region configured to contact a center portion of the protrusion (the region of 6 contacting with the upper surface of 2P, [0049]) having a first thickness greater than a second thickness of a region contacting both side surfaces of the protrusion (6 is thicker at the upper surface of 2P than at the side surfaces of 2P, [0009, 0049, 0067]); and
a gate electrode layer (7, [0095]) disposed on the gate insulation layer (6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Tarui (US 2012/0112266) in view of Wang et al. (CN 111933685A; hereinafter ‘Wang’).
Regarding claim 1, Tarui teaches a power semiconductor device (FIG. 18, [0085]), comprising:
a semiconductor layer (2, [0087]) having a first conductivity type (n-type, [0089]) and configured to include a protrusion (protrusion of 2, [0091]; hereinafter ‘2P’) formed from an upper region of the semiconductor layer to partially protrude upward (shown in FIG. 18);
a shielding region (27, [0090]), having a second conductivity type opposite to the first conductivity type (p-type, [0085, 0101]);
a gate insulation layer (6, [0086]) disposed on the semiconductor layer (2) and configured to cover the protrusion (2P) and to be in contact with the shielding region (27); and
a gate electrode layer (7, [0095]), disposed on the gate insulation layer (6).
Tarui does not teach the power semiconductor device comprising the shielding region disposed within the protrusion, and configured to contact a top surface of the protrusion.
Wang teaches a power semiconductor device (200, Figure 2, [0068]) comprising the shielding region (207) disposed within the protrusion (206), and configured to contact a top surface of the protrusion (207 is formed in the surface of 206, with an upper surface of 207 flush with a top surface of 206).
As taught by Wang, one of ordinary skill in the art would utilize and modify the above teaching into Tarui to obtain and achieve the power semiconductor device comprising the shielding region disposed within the protrusion, and configured to contact a top surface of the protrusion as claimed, because it reduces electric field stress at the gate oxide layer and improves device reliability, while maintaining conduction characteristics [0082].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wang in combination with Tarui due to above reason.
Regarding claim 2, Tarui in view of Wang teaches the power semiconductor device according to claim 1, further comprising:
a well region (Tarui: 3, FIG. 18, [0092]) having the second conductivity type (p-type) and disposed on at least one side of the protrusion (2P) within the semiconductor layer (2);
a source region (4, [0093]) having the first conductivity type (n-type, [0040, 0080]) and disposed in the well region (3) and configured to contact a top surface of the semiconductor layer (2, 4 is formed in a surface of 3 and extends to and contacts a top surface of 2, [0040]); and
a well contact region (5, [0093]) having the second conductivity type (5 electrically connects to 3, and thus corresponds to a well contact region of the same conductivity type, i.e., the second conductivity type, [0040]) and disposed at one side of the source region (4) within the well region (3) and configured to contact a top surface of the semiconductor layer (2, 5 is formed on a surface of 2 adjacent to 4 and contacts the top surface of 2, [0040]).
Regarding claim 3, Tarui in view of Wang teaches the power semiconductor device according to claim 2, wherein: the gate electrode layer (Tarui: 7, FIG. 18) extends to cover a partial region of the source region (4) while entirely covering the protrusion (2P).
Regarding claim 10, Tarui teaches a power semiconductor device (FIG. 18, [0085]), comprising:
a semiconductor layer (2, [0087]) comprising silicon carbide (SiC) (SiC, [0057, 0060]) having a first conductivity type (n-type, [0089]);
a shielding region (27, [0090]) having a second conductivity type opposite to the first conductivity type (p-type, [0085, 0101]);
a well region (3, [0092]) having the second conductivity type (p-type) and disposed on at least one side of the shielding region (27) in the semiconductor layer (2);
a source region (4, [0093]) having the first conductivity type (n-type, [0040, 0080]) and disposed in the well region (3) to contact a top surface of the semiconductor layer (2, 4 is formed in a surface of 3 and extends to and contacts a top surface of 2, [0040]);
a gate insulation layer (6, [0086]) disposed in the semiconductor layer (2) and configured to cover the shielding region (27); and
a gate electrode layer (7, [0095]) configured to cover the shielding region (27) and disposed on the gate insulation layer (6) and extending to the source region (4).
Tarui does not teach the power semiconductor device comprising the shielding region disposed in the semiconductor layer so as to be in contact with a top surface of the semiconductor layer.
Wang teaches a power semiconductor device (200, Figure 2, [0068]) comprising the shielding region (207) disposed in the semiconductor layer (206) so as to be in contact with a top surface of the semiconductor layer (207 is formed in the surface of 206, with an upper surface of 207 flush with a top surface of 206).
As taught by Wang, one of ordinary skill in the art would utilize and modify the above teaching into Tarui to obtain and achieve the power semiconductor device comprising the shielding region disposed in the semiconductor layer so as to be in contact with a top surface of the semiconductor layer as claimed, because it reduces electric field stress at the gate oxide layer and improves device reliability, while maintaining conduction characteristics [0082].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wang in combination with Tarui due to above reason.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Tarui (US 2012/0112266) in view of Wang (CN 111933685A) as applied to claims 1 & 2 above, and further in view of Tarui (US 2016/0225905; hereinafter ‘Tarui905’)
Regarding claim 4, Tarui in view of Wang teaches the power semiconductor device according to claim 2, but does not teach the power semiconductor device wherein the gate electrode layer comprises: a plurality of sub-gate electrodes isolated from each other and configured to expose at least a portion of the protrusion.
Tarui905 teaches a power semiconductor device (FIG. 7, [0114]) wherein the gate electrode layer (8b, [0115]) comprises: a plurality of sub-gate electrodes (8b formed in separated portions on opposite sides of 7b) isolated from each other (shown in FIG. 7) and configured to expose (8b is absent in the central region) at least a portion of the protrusion (the protrusion of 2; hereinafter ‘2PR’).
As taught by Tarui905, one of ordinary skill in the art would utilize and modify the above teaching into Tarui in view of Wang to obtain and achieve the power semiconductor device wherein the gate electrode layer comprises: a plurality of sub-gate electrodes isolated from each other and configured to expose at least a portion of the protrusion as claimed, because omitting the gate electrode in the midsection of the JFET region reduces electric field strength and improves reliability of the gate insulating film [0116].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Tarui905 in combination with Tarui in view of Wang due to above reason.
Regarding claim 5, Tarui in view of Wang and Tarui905 teaches the power semiconductor device according to claim 4, Tarui in view of Wang does not teach the power semiconductor device wherein: the plurality of sub-gate electrodes are disposed symmetrically with each other with respect to a center portion of the protrusion.
Tarui905 teaches the power semiconductor device wherein: the plurality of sub-gate electrodes are disposed symmetrically with each other with respect to a center portion of the protrusion (8b is formed on opposite sides of 2PR with the midsection left unoccupied, thereby forming a symmetric arrangement about the center of 2PR, FIG. 7, [0115]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Tarui905 to obtain and achieve the power semiconductor device wherein: the plurality of sub-gate electrodes are disposed symmetrically with each other with respect to a center portion of the protrusion as claimed, because a symmetric layout provides uniform electric field distribution and balanced device operation across the structure, and reducing electric field strength and improving reliability are desirable for device performance [0116].
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Tarui (US 2012/0112266) in view of Wang (CN 111933685A) as applied to claim 1 above, and further in view of Ryu (US 2011/0254016).
Regarding claim 6, Tarui in view of Wang teaches the power semiconductor device according to claim 1, wherein the semiconductor layer (Tarui: 2 of FIG. 18, which is implemented as 23, [0087]) comprises:
a drift region (a lower portion of 23 underlying the protrusion, [0004, 0039]; hereinafter ‘23D’) comprising impurities of the first conductivity type (23 including first conductivity type impurities, e.g., n-type, [0052]), the impurities being distributed at a first concentration (a concentration of 23D, since 23 having two-staged impurity concentration, [0051, 0081]); and
a junction field effect transistor (JFET) region (an upper portion of 23 including the protrusion region, [0005, 0048]; hereinafter ‘23P’) comprising the impurities of the first conductivity type (23 including first conductivity type impurities, e.g., n-type) being distributed at a second concentration (a concentration of 23P, since 23 having two-staged impurity concentration), the second concentration having a density greater than the first concentration, the JFET (23P) being disposed on the drift region (23D).
Tarui in view of Wang does not teach the power semiconductor device wherein the semiconductor layer comprises the second concentration having a density greater than the first concentration.
Ryu teaches a power semiconductor device (Figure 2A, [0041]) wherein the semiconductor layer (12 and 26, [0042]) comprises the second concentration having a density greater than the first concentration (the JFET region 26 having the high impurity concentration than that of the drift layer 12).
As taught by Ryu, one of ordinary skill in the art would utilize and modify the above teaching into Tarui in view of Wang to obtain and achieve the power semiconductor device wherein the semiconductor layer comprises the second concentration having a density greater than the first concentration as claimed, because such a configuration reduces depletion effects and improves current conduction, thereby reducing on-state resistance [0010, 0040].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Ryu in combination with Tarui in view of Wang due to above reason.
Regarding claim 7, Tarui in view of Wang and Ryu teaches the power semiconductor device according to claim 6, Tarui in view of Wang does not teach the power semiconductor device wherein the semiconductor layer further comprises: a first impurity region disposed in the JFET region and configured to have a third concentration of the first conductivity type and having a density greater than the second concentration.
Ryu teaches the power semiconductor device wherein the semiconductor layer (12 and 26, Figure 2A, [0041-0042]) further comprises: a first impurity region disposed in the JFET region (26 is provided adjacent sidewalls of 20, and includes portions extending along the sidewalls as well as portions located away from the sidewalls, [0043]) and configured to have a third concentration of the first conductivity type (26 is disclosed as having a non-uniform carrier concentration, such that portions of the region have different concentration levels depending on spatial location, including portions having higher concentration than other portions within the region, [0042-0043]) and having a density greater than the second concentration (portion of 26 having higher concentration than other portions within the region would have been understood as regions having a concentration greater than surrounding portion of 26).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Ryu to obtain and achieve the power semiconductor device wherein the semiconductor layer further comprises: a first impurity region disposed in the JFET region and configured to have a third concentration of the first conductivity type and having a density greater than the second concentration as claimed, because impurity concentration distribution within the JFET region is a result-effective variable for reducing resistance and improving current conduction [0040, 0042-0043].
Regarding claim 8, Tarui in view of Wang and Ryu teaches the power semiconductor device according to claim 7, Tarui in view of Wang does not teach the power semiconductor device wherein the semiconductor layer further comprises: a second impurity region including the third concentration of the first conductivity type disposed on at least one side of the first impurity region and arranged lower than the first impurity region by a height of the protrusion.
Ryu teaches the power semiconductor device wherein the semiconductor layer (12 and 26, Figure 2A, [0041-0042]) further comprises: a second impurity region including the third concentration of the first conductivity type (26a disposed beneath 20a and having a higher carrier concentration, [0043]) disposed on at least one side of the first impurity region (26 includes portions extending laterally beneath and adjacent to other portions of the region, thereby providing regions disposed at least on one side of another impurity region within 26, [0043]) and arranged lower than the first impurity region by a height of the protrusion (26a is disposed beneath 20a, and thus is vertically lower than portion of 26 located adjacent the sidewalls of 20, corresponding to a lower position relative to the protrusion, [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Ryu to obtain and achieve the power semiconductor device wherein the semiconductor layer further comprises: a second impurity region including the third concentration of the first conductivity type disposed on at least one side of the first impurity region and arranged lower than the first impurity region by a height of the protrusion as claimed, because arranging impurity regions at different vertical positions within the JFET region reduces depletion and improves current conduction, thereby reducing on-state resistance [0040].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 4/20/26
Prosecution Insights