DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 6/29/2026. Claims 1-17 are pending in this application. Claims 1, 6, and 9-10 are amended. Claims 11-17 remain withdrawn.
Claim Objections
Claims 2 and 9 are objected to because of the following informalities:
In claim 2, line 7, “to contact a top surface of the” should read --to contact the top surface of the-- (emphasis added).
In claim 9, lines 7-8, “of the protrusion second regions” should read --of the protrusion and second regions--, line 8, “the top surfaces of the protrusion” should read –the top surface of the protrusion--, and line 13, “a thickness of the second region” should read –a thickness of the second regions-- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (CN 111933685A; hereinafter ‘Wang’).
Regarding claim 1, Wang teaches a power semiconductor device (200, Figure 2, [0068]), comprising:
a semiconductor layer (a semiconductor layer including 202 and 206, [0068]; hereinafter ‘SL’) having a first conductivity type (a first conductivity type, [0070-0072]) and configured to include a protrusion (206, [0068]) formed from an upper region of the semiconductor layer to partially protrude upward (206 formed from an upper of SL to partially protrude upward);
a shielding region (207, [0068]), having a second conductivity type (a second conductivity type, [0074]) opposite to the first conductivity type (the second conductivity type and the first conductivity type are opposite, [0081]);
a gate insulation layer (208, [0068]) disposed on the semiconductor layer (SL) and configured to cover the protrusion (206) and to be in contact with the shielding region (207); and
a gate electrode layer (209, [0068]), disposed on the gate insulation layer (208),
wherein the protrusion (206) includes a first region (a central portion of 206; hereinafter ‘206C’) disposed at the center portion (206C is located at the center portion of 206) and second regions (portions of 206 located on opposite sides of 206C hereinafter ‘206E’) disposed at both sides of the first region (206E are located on respective sides of 206C), and
wherein the shielding region (207) is disposed in the first region and not in the second regions (207 is disposed in 206C and does not extend into 206E).
Regarding claim 2, Wang teaches the power semiconductor device according to claim 1, further comprising:
a well region (203, FIG. 2, [0068]) having the second conductivity type (the second conductivity type, [0071]) and disposed on at least one side of the protrusion (2P) within the semiconductor layer (230 are disposed within SL on both sides of 206);
a source region (204, FIG. 2, [0068]) having the first conductivity type (the first conductivity type, [0072]) and disposed in the well region (204 is disposed in 203) and configured to contact a top surface of the semiconductor layer (204 extends to and contacts a top surface of SL, FIG. 2); and
a well contact region (205, [0068]) having the second conductivity type (the second conductivity type, [0073]) and disposed at one side of the source region within the well region (205 is disposed in 203 beside 204) and configured to contact a top surface of the semiconductor layer (205 extends to and contacts the top surface of SL, FIG. 2).
Regarding claim 3, Wang teaches the power semiconductor device according to claim 2, wherein: the gate electrode layer (209, FIG. 2) extends to cover a partial region of the source region (4) while entirely covering the protrusion (209 extends over a portion of 204 while entirely covering 206).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (CN 111933685A) in view of Tarui (US 2016/0225905; hereinafter ‘Tarui905’)
Regarding claim 4, Wang teaches the power semiconductor device according to claim 2, but does not teach the power semiconductor device wherein the gate electrode layer comprises: a plurality of sub-gate electrodes isolated from each other and configured to expose at least a portion of the protrusion.
Tarui905 teaches a power semiconductor device (FIG. 7, [0114]) wherein the gate electrode layer (8b, [0115]) comprises: a plurality of sub-gate electrodes (8b formed in separated portions on opposite sides of 7b) isolated from each other (shown in FIG. 7) and configured to expose (8b is absent in the central region) at least a portion of the protrusion (the protrusion of 2; hereinafter ‘2PR’).
As taught by Tarui905, one of ordinary skill in the art would utilize and modify the above teaching into Wang to obtain and achieve the power semiconductor device wherein the gate electrode layer comprises: a plurality of sub-gate electrodes isolated from each other and configured to expose at least a portion of the protrusion as claimed, because omitting the gate electrode in the midsection of the JFET region reduces electric field strength and improves reliability of the gate insulating film [0116].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Tarui905 in combination with Wang due to the above reason.
Regarding claim 5, Wang in view of Tarui905 teaches the power semiconductor device according to claim 4, Wang does not teach the power semiconductor device wherein: the plurality of sub-gate electrodes are disposed symmetrically with each other with respect to a center portion of the protrusion.
Tarui905 teaches the power semiconductor device wherein: the plurality of sub-gate electrodes are disposed symmetrically with each other with respect to a center portion of the protrusion (8b is formed on opposite sides of 2PR with the midsection left unoccupied, thereby forming a symmetric arrangement about the center of 2PR, FIG. 7, [0115]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Tarui905 to obtain and achieve the power semiconductor device wherein: the plurality of sub-gate electrodes are disposed symmetrically with each other with respect to a center portion of the protrusion as claimed, because a symmetric layout provides uniform electric field distribution and balanced device operation across the structure, and reducing electric field strength and improving reliability are desirable for device performance [0116].
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (CN 111933685A) in view of Ryu (US 2011/0254016).
Regarding claim 6, Wang teaches the power semiconductor device according to claim 1, wherein the semiconductor layer (SL, FIG. 2) comprises:
a drift region (202, [0068]) comprising impurities of the first conductivity type, the impurities being distributed at a first concentration (first conductivity type drift layer 202 having an ion doping concentration of approximately 1x1014 to 5x1016cm-3, [0070]); and
a junction field effect transistor (JFET) region (JFET region 206, which also corresponds to the protrusion recited in claim1, is the first conductivity type region located between well regions 203 and formed in an upper portion of 202, [0068, 0070-0072]) comprising the impurities of the first conductivity type being distributed at a second concentration, the JFET region being disposed on the drift region (206 comprises the first conductivity type impurities distributed at a second concentration because it is a portion of 202, [0070-0072]).
Wang does not teach the second concentration of JFET region having a density greater than the first concentration of the drift region.
Ryu teaches a power semiconductor device (Figure 2A, [0041]) wherein the semiconductor layer (12 and 26, [0042]) comprises the second concentration having a density greater than the first concentration (first conductivity type JFET limiting region 26 having a higher impurity concentration than drift layer 12, [0042]).
As taught by Ryu, one of ordinary skill in the art would utilize and modify the above teaching into Wang to obtain and achieve the power semiconductor device wherein the semiconductor layer comprises the second concentration having a density greater than the first concentration as claimed, because the higher concentration JFET region reduces the depletion region in the JFET gap and shortens the current path, thereby reducing the on state resistance of the device [0040, 0065-0066].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Ryu in combination with Wang due to the above reason.
Regarding claim 7, Wang in view of Ryu teaches the power semiconductor device according to claim 6, Wang does not teach the power semiconductor device wherein the semiconductor layer further comprises: a first impurity region disposed in the JFET region and configured to have a third concentration of the first conductivity type and having a density greater than the second concentration.
Ryu teaches the power semiconductor device wherein the semiconductor layer (12 and 26, Figure 2A, [0041-0042]) further comprises: a first impurity region disposed in the JFET region (26 is provided adjacent sidewalls of 20, and includes portions extending along the sidewalls as well as portions located away from the sidewalls, [0043]) and configured to have a third concentration of the first conductivity type (26 is disclosed as having a non-uniform carrier concentration, such that portions of the region have different concentration levels depending on spatial location, including portions having higher concentration than other portions within the region, [0042-0043]) and having a density greater than the second concentration (portion of 26 having higher concentration than other portions within the region would have been understood as regions having a concentration greater than surrounding portion of 26).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Ryu to obtain and achieve the power semiconductor device wherein the semiconductor layer further comprises: a first impurity region disposed in the JFET region and configured to have a third concentration of the first conductivity type and having a density greater than the second concentration as claimed, because impurity concentration distribution within the JFET region is a result-effective variable for reducing resistance and improving current conduction [0040, 0042-0043].
Regarding claim 8, Wang and Ryu teaches the power semiconductor device according to claim 7, Wang does not teach the power semiconductor device wherein the semiconductor layer further comprises: a second impurity region including the third concentration of the first conductivity type disposed on at least one side of the first impurity region and arranged lower than the first impurity region by a height of the protrusion.
Ryu teaches the power semiconductor device wherein the semiconductor layer (12 and 26, Figure 2A, [0041-0042]) further comprises: a second impurity region including the third concentration of the first conductivity type (26a disposed beneath 20a and having a higher carrier concentration, [0043]) disposed on at least one side of the first impurity region (26 includes portions extending laterally beneath and adjacent to other portions of the region, thereby providing regions disposed at least on one side of another impurity region within 26, [0043]) and arranged lower than the first impurity region by a height of the protrusion (26a is disposed beneath 20a, and thus is vertically lower than portion of 26 located adjacent the sidewalls of 20, corresponding to a lower position relative to the protrusion, [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Ryu to obtain and achieve the power semiconductor device wherein the semiconductor layer further comprises: a second impurity region including the third concentration of the first conductivity type disposed on at least one side of the first impurity region and arranged lower than the first impurity region by a height of the protrusion as claimed, because arranging impurity regions at different vertical positions within the JFET region reduces depletion and improves current conduction, thereby reducing on-state resistance [0040].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Tarui (US 2012/0112266; hereinafter ‘Tarui266’) in view of Sdrulla et al. (US 2023/0022394; hereinafter ‘Sdrulla’).
Regarding claim 9, Tarui teaches a power semiconductor device (FIG. 18, [0085]), comprising:
a semiconductor layer (2, [0087]) comprising silicon carbide (SiC) (SiC, [0057, 0060]), the semiconductor layer (2) including a protrusion (protrusion of 2, [0091]; hereinafter ‘2P’) formed upwards from a partial portion of an upper region of the semiconductor layer (shown in FIG. 18);
a gate insulation layer (6, [0086]) disposed on the semiconductor layer (2) disposed to cover the protrusion (2P), and comprising a first region (a center portion of 6, Figure 2; hereinafter ‘6C’) configured to contact a center portion of a top surface of the protrusion (6C contacting with the center portion of the upper surface of 2P) second regions (opposite end portions of 6, Figure 2; hereinafter ‘6E’) contacting both side portions of the top surfaces of the protrusion (6E contacting with both side portions of the upper surface of 2P); and
a gate electrode layer (7, [0095]) disposed on the gate insulation layer (6).
Tarui does not teach the power semiconductor device wherein a bottom surface of the first region is located at a lower level than the bottom surface of the second regions, and a top surface of the first region is located at a higher level than the top surfaces of the second regions, so that a thickness of the first region is greater than a thickness of the second region.
Sdrulla teaches a power semiconductor device (100F, FIG. 1F, [0131])
wherein a bottom surface of the first region (a bottom surface of the center portion of 118T, [0044]) is located at a lower level than the bottom surface of the second regions (a bottom surface of the opposite end portions of 118T), and
a top surface of the first region (a top surface of the center portion of 118R, [0077]) is located at a higher level than the top surfaces of the second regions (top surfaces of the opposite end portions of 118R),
so that a thickness of the first region is greater than a thickness of the second region (a thickness of the center portions 118T and 118R is greater than the thickness of the opposite end portions of 118T and 118R, FIG. 1F).
As taught by Sdrulla, one of ordinary skill in the art would utilize and modify the above teaching into Tarui to obtain and achieve the power semiconductor device wherein a bottom surface of the first region is located at a lower level than the bottom surface of the second regions, and a top surface of the first region is located at a higher level than the top surfaces of the second regions, so that a thickness of the first region is greater than a thickness of the second region as claimed, because forming a thicker central insulation region extending both above and below the adjacent insulation regions reduces the electric field and gate-to-drain capacitance at the center of the JFET region, thereby improving gate dielectric reliability [0079].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Sdrulla in combination with Tarui due to the above reason.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Tarui (US 2012/0112266) in view of Wang (CN 111933685A).
Regarding claim 10, Tarui teaches a power semiconductor device (FIG. 18, [0085]), comprising:
a semiconductor layer (2, [0087]) comprising silicon carbide (SiC) (SiC, [0057, 0060]) having a first conductivity type (n-type, [0089]);
a shielding region (27, [0090]) having a second conductivity type opposite to the first conductivity type (p-type, [0085, 0101]);
a well region (3, [0092]) having the second conductivity type (p-type) and disposed on at least one side of the shielding region (27) in the semiconductor layer (2);
a source region (4, [0093]) having the first conductivity type (n-type, [0040, 0080]) and disposed in the well region (3) to contact a top surface of the semiconductor layer (2, 4 is formed in a surface of 3 and extends to and contacts a top surface of 2, [0040]);
a gate insulation layer (6, [0086]) disposed in the semiconductor layer (2) and configured to cover the shielding region (27); and
a gate electrode layer (7, [0095]) configured to cover the shielding region (27) and disposed on the gate insulation layer (6) and extending to the source region (4).
Although, Tarui’s embodiment of FIG. 18 does not explicitly teach the power semiconductor device wherein a protrusion is not formed on the semiconductor layer.
Tarui, however, separately discloses the power semiconductor device wherein a protrusion is not formed on the semiconductor layer (no protrusion is formed on semiconductor layer 20 corresponding to the semiconductor layer 2, FIG. 26, [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Tarui to obtain and achieve the power semiconductor device wherein a protrusion is not formed on the semiconductor layer as claimed, because a thicker gate insulation layer in the JFET region may be used instead of a semiconductor protrusion to suppress the electric field applied to the gate insulation layer [0044-0045].
Tarui does not teach the power semiconductor device comprising the shielding region disposed in the semiconductor layer so as to be in contact with a top surface of the semiconductor layer.
Wang teaches a power semiconductor device (200, Figure 2, [0068]) comprising the shielding region (207) disposed in the semiconductor layer (206) so as to be in contact with a top surface of the semiconductor layer (207 is formed in the surface of 206, with an upper surface of 207 flush with a top surface of 206).
As taught by Wang, one of ordinary skill in the art would utilize and modify the above teaching into Tarui to obtain and achieve the power semiconductor device comprising the shielding region disposed in the semiconductor layer so as to be in contact with a top surface of the semiconductor layer as claimed, because it reduces electric field stress at the gate oxide layer and improves device reliability, while maintaining conduction characteristics [0082].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Wang in combination with Tarui due to above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Applicant submits, in page 8 of Remark, that
“According to amended claim 1, the shielding region is partially disposed only at the
center portion of the protrusion. By comparison, the second conductive type region (27) of Tarui (US 2012/0112266) and the shielding region (207) of Wang (CN 111933685) cover the whole upper region of the protrusion. Thus, the cited art fails to teach or suggest, either alone or in combination, every feature of claim 1. For similar reasons, the rejection of claim 10 is overcome”.
The examiner respectfully disagrees.
Regarding claim 1, Wang’s shielding region 207 is disposed within a central portion of protrusion 206 and does not extend into the opposite end portions of the protrusion, as shown in FIG. 2. Accordingly, Applicant’s assertion that Wang’s shielding region 207 covers the whole upper region of the protrusion is not consistent with Wang’s disclosed structure.
Regarding claim 10, Applicant’s argument concerning the location of the shielding region within a protrusion is not responsive to the amended limitation of claim 10. Unlike claim 1, claim 10 recites that a protrusion is not formed on the semiconductor layer. Tarui expressly teaches this limitation by disclosing that epitaxial layer 20 has no protrusion (FIG. 26, [0044]). Accordingly, Applicant’s assertion that the rejection of claim 10 is overcome “for similar reasons” is not persuasive.
Therefore, the amendments and arguments do not overcome the rejections of claims 1 and 10.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 8/31/26
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