DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on 11/14/2023 and 3/24/2025 . The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Objections Claim 1 objected to because of the following informalities: the claim appears to have a typographical error " a drift layer disposed in the semiconductor die the between the first conduction terminal and the second conduction terminal ". For the purpose of examination, the examiner will interpret the above limitation as " a drift layer disposed in the semiconductor die the between the first conduction terminal and the second conduction terminal". Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1- 4, 6 , 8 - 1 0 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bhalla US 2015/0035005. Re claim 1 , Bhalla teaches a semiconductor device (fig2) comprising: a switching device (1 9 0, fig2A, [27]) comprising: a control terminal (120, fig2A, [26]), a first conduction terminal (170, fig2A, [27]) disposed on a first surface of a semiconductor die (top surface of 1 1 0, fig2A, [26]), a second conduction terminal (101, fig2A, [26]) disposed on a second surface of the semiconductor die (bottom surface of 10 3 , fig2A, [26]), the second surface being opposite the first surface, and a drift layer (110, fig2A, [26]) disposed in the semiconductor die the between the first conduction terminal (1 7 0, fig2A, [27]) and the second conduction terminal (101, fig2A, [26]); a cathode structure (structure around 180, fig2A, [27]) disposed in the semiconductor die and having a cathode pad (180, fig2A, [27]) disposed on the first surface of the semiconductor die, wherein the cathode pad (180, fig2A, [27]) is electrically connected to the drift layer (110, fig2A, [26]), and a termination structure (structure around 160 between 170 and 180, fig2A) disposed between the switching device (190, fig2A, [27]) and the cathode structure (structure around 180, fig2A, [27]). Re claim 2 , Bhalla teaches the semiconductor device of claim 1, wherein the cathode structure (structure around 180, fig2A, [27]) comprises a cathode contact (130’, fig2A, [27]) disposed in contact with the drift layer (110, fig2A, [26]) and electrically coupled to the cathode pad (180, fig2A, [27]). Re claim 3 , Bhalla teaches the semiconductor device of claim 2, wherein the cathode contact (130’, fig2A, [27]) is disposed at the bottom of a trench formed in the drift layer (trench in 110 holding 130, fig2A). Re claim 4 , Bhalla teaches the semiconductor device of claim 1, where the termination structure is a voltage termination structure configured to prevent the propagation of an electric field (fig2A, 2B). Re claim 6 , Bhalla teaches the semiconductor device of claim 4, where the termination structure comprises a floating field ring (160, fig2A, [33]) disposed in the drift layer (110, fig2A, [26]). Re claim 8 , Bhalla teaches the semiconductor device of claim 1, wherein the cathode pad (180, fig2A, [27]) operates as a first terminal of a diode (fig2B) and the first conduction terminal (170, fig2A, [27]) operates as a second terminal of the diode. Re claim 9 , Bhalla teaches the semiconductor device of claim 8, wherein when the switching device is turned on and a voltage across the first conduction terminal and the second conduction terminal has a first polarity, a first current flows between the first conduction terminal and the second conduction terminal and the diode is reversed biased, and wherein when a voltage across the first conduction terminal and the cathode pad has a second polarity opposite the first polarity, the diode is forward biased (fig2B). Re claim 10 , Bhalla teaches the semiconductor device of claim 8, wherein the diode is a pn-junction diode (199, fig2B) having an anode (170, fig2A, [27]) corresponding to a well ( p-type 125, fig2A, [26]) of the switching device and a cathode (180, fig2A, [27]) corresponding to the drift layer ( N-type 110, fig2A, [26]) , the well having a doping type opposite that of the drift layer. Re claim 19 , Bhalla teaches the semiconductor device of claim 1, wherein the switching device is a vertical Insulated Gate Bipolar Transistor (190, fig2A, [27]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Bhalla US 2015/0035005 in view of Majumdar et al. US 2002/0153586. Re claim 7 , Bhalla teaches the semiconductor device of claim 4, where the termination structure comprises a field ring plate (160, fig2A, [33]) disposed above the drift layer (110, fig2A, [26]) . Bhalla does not explicitly show an insulating material disposed between the field plate and the drift layer. Majumdar teaches a termination structure (15, fig1, [43]) between the IGBT region (20, fig1, [43]) and diode region (21, fig1, [43]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bhalla and Majumdar to add a partition member between the IGBT region and diode region (between Bhalla 125 and 160 or between 160 and 130’ in fig2A). the motivation to do so is to suppress occurrence of latchup and interference between two regions (Majumdar, [46, 49]). Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Bhalla US 2015/0035005 in view of Takahashi US 2005/0045960. Re claim 11 , Bhalla teaches the semiconductor device of claim 8, a cathode (130’, fig2A, [27]) corresponding to the drift layer (110, fig2A, [26]). Bhalla does not explicitly show the diode is a Schottky barrier diode (SBD) having an anode corresponding to a Schottky layer electrically coupled to the first conduction terminal and Takahashi teaches using an SBD as the FWD (fig7, [93]) with Schottky junction anode (13, fig7, [93]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bhalla and Takahashi to use SBD as the FWD. the motivation to do so is to reduce density of carriers around the anode and reduce recovery current during transition (Takahashi, [93]). Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Bhalla US 2015/0035005 in view of Chen et al. US 2023/0261119 . Re claim 20 , Bhalla does not explicitly show the semiconductor device of claim 1, wherein the semiconductor die comprises a wide-bandgap semiconductor. Chen teaches using wide band-gap semiconductor such as SiC to replace Si. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bhalla and Chen to use SiC substrate. the motivation to do so is to achieve high breakdown field strength, high thermal conductivity and low power loss(Chen, [3]). Allowable Subject Matter Claim 5 and 12-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim. Specifically, the limitations are material to the inventive concept of the application in hand to increase output current and power handling capability of the power device and reduce snapback . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT XIAOMING LIU whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-0384 . 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