DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 04/14/2024. Claims 1-20 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 01/04/2024.
Oath/Declaration
The oath or declaration filed on 11/14/2023 is acceptable.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/16/2025 and 11/14/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Election/Restrictions
Applicant’s election, with traverse, of Species IV: claims 1-7, 9-15 and 17-19, in the “Response to Election / Restriction Filed” filed on 04/14/2026 is acknowledged. The traversal is on the ground(s) that, search and examination of all the claims may be made without serious burden.
The species require a different field of search (e.g., searching different classes/subclasses or electronic resources or non-patent language, or deploying different search queries); and/or the prior art applicable to one species would not likely be applicable to another species; and/or the species are likely to raise different non-prior art issues under U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
Furthermore, the species require separate classification searches (i.e. (H10B12/482 or G11C5/063 or H10B12/315 or H10B12/485 or H10B12/488 or H10B12/50 or H10B12/09 or H10B12/30) such as there are mutually exclusive features, as indicated in office action 04/08/2026 and these mutually exclusive features are categorized in the separate classes. Additionally, the species require different text searches. The requirement is still deemed proper and is therefore made FINAL.
This office action considers claims 1-20 are thus pending for prosecution, of which, claims 8,16 and 20 are withdrawn, and claims 1-7, 9-15 and 17-19 are examined on their merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 11-15 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHANG et al (US 2022/0139927 A1; hereafter CHANG).
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Regarding claim 1. CHANG discloses a semiconductor memory device comprising:
a substrate (Fig. [1-10], substrate 100, Para [ 0027-0033]) including a cell region (cell region 20, Para [ 0008-0012, 0027-0033]) and a peripheral region (Fig. [1-10], peripheral region 24, Para [ 0008-0012, 0027-0033]);
a cell region isolation layer (cell region isolation film 22, Para [ 0008-0012, 0027-0033]) in the substrate (Fig. [1-10], substrate 100, Para [ 0027-0033]), isolating the cell region (cell region 20, Para [ 0008-0012, 0027-0033]) from the peripheral region (Fig. [1-10], peripheral region 24, Para [ 0008-0012, 0027-0033]);
an isolation active region (cell active regions ACT, Para [ 0032]) surrounded by the cell region isolation layer (cell region isolation film 22, Para [ 0008-0012, 0027-0033]);
a bit line structure (a bit line structure 140ST, Para [ 0069]) on the cell region (cell region 20, Para [ 0008-0012, 0027-0033]), including a cell conductive line (first cell conduction film 141, Para [ 0099]); and
a cell gate electrode (bit line contact 146, Para [ 0175]) in the substrate (Fig. [1-10], substrate 100, Para [ 0027-0033]) of the cell region (cell region 20, Para [ 0008-0012, 0027-0033]), crossing the cell conductive line (first cell conduction film 141, Para [ 0099]).
Regarding claim 2. CHANG discloses the semiconductor memory device of claim 1, CHANG further discloses wherein the cell region isolation layer (Fig [2-3], cell region isolation film 22, Para [ 0008-0012, 0027-0033]) includes a first portion extending in a first direction and a second portion extending in a second direction orthogonal to the first direction, and in a plan view (Fig 2, cell region isolation film 22, Para [ 0008-0012, 0027-0033]), the isolation active region (cell active regions ACT, Para [ 0032]) is in the first portion of the cell region isolation layer and is not in the second portion of the cell region isolation layer (Fig [2-3], Para [ 0034-0037] discloses “Each cell active region ACT may be divided into three portions by two word lines WL extending in the first direction D1. The cell active region ACT may include a storage connection region 103b and a bit line connection region 103a. The bit line connection region 103a may be located at a central portion (e.g., in the third direction D3) of the cell active region ACT, and the storage connection region 103b may be located at the end portion of the cell active region ACT”).
Regarding claim 3. CHANG discloses the semiconductor memory device of claim 2, CHANG further discloses wherein the cell conductive line (first cell conduction film 141, Para [ 0099]) extends in the second direction, and the cell gate electrode (bit line contact 146, Para [ 0175]) extends in the first direction (Fig. [2,6-7], Para [ 0027-0033]).
Regarding claim 4. CHANG discloses the semiconductor memory device of claim 3, CHANG further discloses wherein a portion of the cell conductive line (first cell conduction film 141, Para [ 0099]) overlaps the first portion of the cell region isolation layer (cell region isolation film 22, Para [ 0008-0012, 0027-0033]) in a third direction Fig. [2,6-7]).
Regarding claim 5. CHANG discloses the semiconductor memory device of claim 3, CHANG further discloses wherein a portion of the cell gate electrode (bit line contact 146, Para [ 0175]) overlaps the second portion of the cell region isolation layer in a third direction (cell region isolation film 22, Para [ 0008-0012, 0027-0033]) in a third direction Fig. [2,6-7]).
Regarding claim 6. CHANG discloses the semiconductor memory device of claim 1, CHANG further discloses wherein the cell conductive line (first cell conduction film 141, Para [ 0099]) includes a long sidewall extending in a first direction and a short sidewall extending in a second direction (first cell conduction film 141, Para [ 0099]), and a portion of the cell conductive line (first cell conduction film 141, Para [ 0099]) overlaps the isolation active region in a third direction (cell active regions ACT, Para [ 0032]).
Regarding claim 7. CHANG discloses the semiconductor memory device of claim 6, CHANG further discloses wherein the cell conductive line (first cell conduction film 141, Para [ 0099]) includes a longitudinal end that includes the short sidewall of the cell conductive line (first cell conduction film 141, Para [ 0099]), and the longitudinal end of the cell conductive line (first cell conduction film 141, Para [ 0099]) is on the isolation active region (Fig [6-7], cell active regions ACT, Para [ 0032]).
Regarding claim 11. CHANG discloses a semiconductor memory device comprising:
a substrate (Fig. [1-10], substrate 100, Para [ 0027-0033]) including a cell region (cell region 20, Para [ 0008-0012, 0027-0033]) and a peripheral region (Fig. [1-10], peripheral region 24, Para [ 0008-0012, 0027-0033]);
a cell region isolation layer (elements [105, 22], Para [ 0032, 0043]) in the substrate (Fig. [1-10], substrate 100, Para [ 0027-0033]), including a first sub-region isolation layer (elements [105], Para [ 0032, 0043]) and a second sub-region isolation layer (elements [22], Para [ 0032, 0043]), which are spaced apart from each other in a first direction, and isolating the cell region from the peripheral region (Fig. [1-10], peripheral region 24, Para [ 0008-0012, 0027-0033]);
an isolation active region (cell active regions ACT, Para [ 0032]) between the first sub-region isolation layer (elements [105], Para [ 0032, 0043]) and the second sub-region isolation layer (elements [22], Para [ 0032, 0043]);
a cell conductive line (bit line contact 146, Para [ 0175]) on the cell region (cell region 20, Para [ 0008-0012, 0027-0033]) and extending in the first direction (Fig. [1-10], cell region 20, Para [ 0008-0012, 0027-0033]); and
a cell gate electrode (bit line contact 146, Para [ 0175]) in the substrate (Fig. [1-10], substrate 100, Para [ 0027-0033]) of the cell region (cell region 20, Para [ 0008-0012, 0027-0033]) and extending in a second direction Fig. [1-10], cell region 20, Para [ 0008-0012, 0027-0033]).
Regarding claim 12. CHANG discloses the semiconductor memory device of claim 11, CHANG further discloses wherein the first sub-region isolation layer (elements [105], Para [ 0032, 0043]) is closer to the cell region than the second sub- region isolation layer (elements [22], Para [ 0032, 0043]), and the cell conductive line (bit line contact 146, Para [ 0175]) overlaps the first sub-region isolation layer in a third direction (elements [105], Para [ 0032, 0043]) and does not overlap the second sub-region isolation layer in the third direction (Fig. [1-10], elements [22], Para [ 0032, 0043]).
Regarding claim 13. CHANG discloses the semiconductor memory device of claim 12, CHANG further discloses wherein a portion of the cell conductive line (bit line contact 146, Para [ 0175]) is on the isolation active region (cell active regions ACT, Para [ 0032]).
Regarding claim 14. CHANG discloses the semiconductor memory device of claim 11, CHANG further discloses wherein the cell region includes a plurality of cell active regions ( another plurality cell active regions ACT, Para [ 0032]) defined by a cell element isolation layer ( cell gate capping pattern 113, Para [ 0049]), and a depth from an upper surface of the cell conductive line (bit line contact 146, Para [ 0175]) to a lowermost portion of the cell element isolation layer ( cell gate capping pattern 113, Para [ 0049]) is smaller than that from the upper surface of the cell conductive line (bit line contact 146, Para [ 0175]) to a lowermost portion of the first sub-region isolation layer (elements [105], Para [ 0032, 0043]).
Regarding claim 15. CHANG discloses the semiconductor memory device of claim 11, CHANG further discloses wherein a width of the first sub-region isolation layer (elements [105], Para [ 0032, 0043]) in the first direction is different from that of the second sub-region isolation layer in the first direction (elements [22], Para [ 0032, 0043]), and a depth from an upper surface of the cell conductive line (bit line contact 146, Para [ 0175]) to a lowermost portion of the first sub-region isolation layer (elements [105], Para [ 0032, 0043]) is a same depth the same as that from the upper surface of the cell conductive line (bit line contact 146, Para [ 0175]) to a lowermost portion of the second sub-region isolation layer (elements [22], Para [ 0032, 0043]).
Regarding claim 18. CHANG discloses a semiconductor memory device comprising:
a substrate (Fig. [1-10], substrate 100, Para [ 0027-0033]) including a cell region (cell region 20, Para [ 0008-0012, 0027-0033]) and a peripheral region (Fig. [1-10], peripheral region 24, Para [ 0008-0012, 0027-0033]);
a cell region isolation layer (cell region isolation film 22, Para [ 0008-0012, 0027-0033]) in the substrate (Fig. [1-10], substrate 100, Para [ 0027-0033]), isolating the cell region (cell region 20, Para [ 0008-0012, 0027-0033]) from the peripheral region (Fig. [1-10], peripheral region 24, Para [ 0008-0012, 0027-0033]);
an isolation active region (cell active regions ACT, Para [ 0032]) surrounded by the cell region isolation layer (cell region isolation film 22, Para [ 0008-0012, 0027-0033]);
a plurality of cell conductive lines (a bit line structure 140ST, Para [ 0069]) on the cell region (cell region 20, Para [ 0008-0012, 0027-0033]) and extending in a first direction (cell region 20, Para [ 0008-0012, 0027-0033]);
a plurality of cell gate electrodes (bit line contact 146, Para [ 0175]) in the substrate (Fig. [1-10], substrate 100, Para [ 0027-0033]) of the cell region (cell region 20, Para [ 0008-0012, 0027-0033]) and extending in a second direction; and
a plurality of cell conductive plugs ( contact plug 261 and 262, Para [ 0124]) on a cell conductive line (third cell conduction film 143, Para [ 0056]) of the plurality of cell conductive lines conductive line ( bit line structure 140ST, Para [ 0069]) and respectively connected to the plurality of cell conductive lines ( bit line structure 140ST, Para [ 0069]), wherein each cell conductive line ( bit line structure 140ST, Para [ 0069]) includes a first longitudinal end and a second longitudinal end ( bit line structure 140ST, Para [ 0069]), the first longitudinal end of the each cell conductive line ( bit line structure 140ST, Para [ 0069]) is spaced apart from the second longitudinal end of the each cell conductive line in the first direction ( bit line structure 140ST, Para [ 0069]), the plurality of cell conductive lines ( bit line structure 140ST, Para [ 0069]) include a first cell conductive line and a second cell conductive line (first cell conduction film 141, a second cell conduction film 142, Para [ 0056]), which are adjacent to each other in the second direction (first cell conduction film 141, a second cell conduction film 142, Para [ 0056]), the first longitudinal end of the first cell conductive line (first cell conduction film 141, Para [ 0056]) is on the isolation active region (cell active regions ACT, Para [ 0032]), and the first longitudinal end of the second cell conductive line (second cell conduction film 142, Para [ 0056]) is on the cell region isolation layer (cell region isolation film 22, Para [ 0008-0012, 0027-0033]).
Allowable Subject Matter
Claims 9-10, 17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 9. a peripheral gate structure on the substrate of the peripheral region, including a peripheral gate conductive layer, a peripheral gate capping layer and a peripheral gate spacer; a bit line spacer on a short sidewall of the cell conductive line; and an etch stop layer that extends along a profile of the peripheral gate spacer, an upper surface of the peripheral gate capping layer and an upper surface of the cell region isolation layer, wherein the peripheral gate spacer includes a first peripheral gate spacer and a second peripheral gate spacer, which include their respective materials different from each other, the first peripheral gate spacer is between the peripheral gate conductive layer and the second peripheral gate spacer, and a stacked structure of the bit line spacer is different from that of the peripheral gate spacer.
Claim 10 is objected based on the dependency of claim 9.
Regarding claim 17. wherein each of the first sub-region isolation layer and the second sub-region isolation layer includes a filling isolation layer, and a liner isolation layer extended along sidewalls and a bottom surface of the filling isolation layer.
Regarding claim 19. wherein the plurality of cell conductive plugs includes a first cell conductive plug connected to the first cell conductive line and a second cell conductive plug connected to the second cell conductive line, the first cell conductive plug is connected to the first cell conductive line near the first longitudinal end of the first cell conductive line, and the second cell conductive plug is connected to the second cell conductive line near the second longitudinal end of the second cell conductive line.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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