DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention II, species B, corresponding to claims 15, 17-21, 23 and 25-34, in the reply filed on 4/22/2026 is acknowledged.
Claims 16, 22 and 24 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/22/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15, 17-21 and 23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are between a first side and a second side, for example, it is not clear whether the two sides are adjacent to each other, or facing away from each other.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are between a second source/drain region of claim 17 and a first source/drain region of claim 15.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are between a second source/drain region of claim 17 and a first source/drain region of claim 15.
Claim 20 recites the limitation "the same conductivity type" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are between a first side and a second side, for example, it is not clear whether the two sides are adjacent to each other, or facing away from each other.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 15, 17 and 18, as so far as understood, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Frougier (US 2020/0035569).
Regarding claim 15, Frougier discloses, in FIGS. 1A-1B and in related text, a method comprising:
forming a first semiconductor nanostructure (125 of lower portion 155), a second semiconductor nanostructure (125 of upper portion 150), first dummy nanostructures (130 of lower portion 155), and second dummy nanostructures (130 of upper portion 150), the first semiconductor nanostructure disposed between the first dummy nanostructures, the second semiconductor nanostructure disposed between the second dummy nanostructures (see Frougier, FIGS. 1A-1B, [0021]-[0022]);
forming a first source/drain region (225, 235) adjacent the first semiconductor nanostructure and the second semiconductor nanostructure in a first cross-section (X-X) (see Frougier, FIG. 1I, [0030]);
replacing the first dummy nanostructures with a first gate structure (including gate metal 255), the first gate structure disposed at a first (left) side of the first semiconductor nanostructure (125 of lower portion 155) and a first (left) side of the second semiconductor nanostructure (125 of upper portion 150) in a second cross-section (Y-Y), wherein the first cross-section is different from the second cross-section (see Frougier, FIG. 1K, [0032]); and
after replacing the first dummy nanostructures, replacing the second dummy nanostructures with a second gate structure (including gate metal 270), the second gate structure disposed at a second (right) side of the first semiconductor nanostructure (125 of lower portion 155) and a second side (right) of the second semiconductor nanostructure (125 of upper portion 150) in the second cross-section (Y-Y) (see Frougier, FIG. 1N, [0035]).
Regarding claim 17, Frougier discloses the method of claim 15.
Frougier discloses forming a second source/drain region (225, 235) adjacent the first semiconductor nanostructure (125 of lower portion 155) and the second semiconductor nanostructure (125 of upper portion 150) in the first cross-section (X-X) (see Frougier, FIG. 1I, [0030]).
Regarding claim 18, Frougier discloses the method of claim 15.
Frougier discloses forming a second source/drain region (225, 235) adjacent the second semiconductor nanostructure (125 of upper portion 150) (see Frougier, FIG. 1I, [0030]); and
forming an isolation dielectric (240, 280) over the first source/drain region (225, 235), the second source/drain region (225, 235), the first gate structure (including gate metal 255), and the second gate structure (including gate metal 270) (see Frougier, FIG. 1O, [0030], [0036]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Frougier in view of Fulford (US 2023/0163185).
Regarding claim 19, Frougier discloses the method of claim 18.
Frougier discloses forming a via (285, 290) through the isolation dielectric (280) (see Frougier, FIG. 1O, [0036]).
Frougier does not explicitly disclose the via connected to the second source/drain region.
Fulford teaches the via (117) connected to the second source/drain region (115) (see Fulford, FIG. 1B, [0055]).
Frougier and Fulford are analogous art because they both are directed to transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Frougier with the features of Fulford because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Frougier to include the via connected to the second source/drain region, as taught by Fulford, to form vertical contact structure to source/drain region (see Fulford, [0055]).
Allowable Subject Matter
Claim 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 21 and 23 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 25-34 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, Frougier, discloses wherein the first semiconductor nanostructure and the second semiconductor nanostructure are of substantially pure silicon. The prior art of records, individually or in combination, do not disclose nor teach “wherein the first semiconductor nanostructure and the second semiconductor nanostructure have the same conductivity type” in combination with other limitations as recited in claim 20.
The prior art of record, Frougier, discloses a method comprising: forming a first semiconductor nanostructure and a second semiconductor nanostructure, the second semiconductor nanostructure being vertically stacked over the first semiconductor nanostructure; forming a first source/drain region adjacent the first semiconductor nanostructure and the second semiconductor nanostructure in a first cross-section; forming a first gate structure at a first side of the first semiconductor nanostructure and a first side of the second semiconductor nanostructure in a second cross-section, wherein the first cross-section is different from the second cross-section; forming a second gate structure at a second side of the first semiconductor nanostructure and a second side of the second semiconductor nanostructure in the second cross-section; The prior art of record, Fulford, teaches forming a third semiconductor nanostructure and a fourth semiconductor nanostructure, the third semiconductor nanostructure being vertically stacked over the second semiconductor nanostructure, the fourth semiconductor nanostructure being vertically stacked over the third semiconductor nanostructure; forming a second source/drain region adjacent the third semiconductor nanostructure and the fourth semiconductor nanostructure in the first cross-section; forming a third gate structure at a third side of the third semiconductor nanostructure and a third side of the fourth semiconductor nanostructure in the second cross-section. The prior art of records, individually or in combination, do not disclose nor teach “forming a fourth gate structure at a fourth side of the third semiconductor nanostructure and a fourth side of the fourth semiconductor nanostructure in the second cross-section” in combination with other limitations as recited in claim 21.
The prior art of record, Fulford, discloses a method comprising: forming a first semiconductor nanostructure and a second semiconductor nanostructure, the first semiconductor nanostructure and the second semiconductor nanostructure being vertically stacked over a substrate; forming a first source/drain region and a second source/drain region, the first semiconductor nanostructure disposed between the first source/drain region and the second source/drain region, the second semiconductor nanostructure disposed between the first source/drain region and the second source/drain region; forming a first isolation dielectric over the first source/drain region, the second source/drain region, the first semiconductor nanostructure, and the second semiconductor nanostructure; forming a third semiconductor nanostructure and a fourth semiconductor nanostructure, the third semiconductor nanostructure and the fourth semiconductor nanostructure being vertically stacked over the first isolation dielectric; forming a third source/drain region, a fourth source/drain region, wherein the third semiconductor nanostructure is disposed between the third source/drain region and the fourth source/drain region. The prior art of records, individually or in combination, do not disclose nor teach “forming a fifth source/drain region, wherein the fourth semiconductor nanostructure is disposed between the third source/drain region and the fifth source/drain region; forming a second isolation dielectric between the fourth source/drain region and the fifth source/drain region ” in combination with other limitations as recited in claim 25.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811
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