DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of “Group I (Claims 1-10)” in the reply filed on 04/16/2026, is acknowledged.
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2,5-6 and 8-10 are rejected under 35 U.S.C. 103 as being obvious over US 2022/0246562 A1; Hou et al.; 08/2022; (“562”) in view of US 2021/0202382 A1; Okina; 07/2021; (“382”).
Regarding Claim 1. 562 teaches in Figs. 1 and 2A about a method of forming a semiconductor structure, comprising:
forming first semiconductor devices (Fig. 1, item 920) over, on or in a first substrate (Fig. 1, item 908, wherein items 920 are over or on item 908);
forming first dielectric material layers (Fig. 1, items 290 or 960) embedding first metal interconnect structures (Fig. 1, items 980) over the first semiconductor devices (Fig. 1, items 980 are over item 920), wherein the first metal interconnect structures are electrically connected to the first semiconductor devices (Fig. 1, “the first metal interconnect structures 980 can be electrically connected to the first semiconductor devices 920”, [0034], Ln. 6-8);
forming a first bonding-level dielectric layer (Fig. 1, items 962 and 990) comprising a layer stack including a first silicate glass layer (Fig. 1, item “962 can include … silicon oxynitride”, [0036], Ln. 7-8) and a first dielectric bonding material layer (Fig. 1, item “dielectric layer 990”, [0036], Ln. 3) over the first dielectric material layers (Fig. 1, item 990 is over item 962);
forming via cavities (Fig. 2A, item 91, Examiner interprets “first pad cavity” item 91 to be considered also a via cavity, since the cavity fully penetrates two layers) through the first dielectric bonding material layer and the first silicate glass layer (Fig. 2A, item cavity 91 fully penetrates layer items 962 and 990).
562 does not teach about a method of forming a semiconductor structure, comprising:
converting the via cavities into integrated pad-and-via cavities by performing a selective etch process that etches a material of the first dielectric bonding material layer selective to a material of the first silicate glass layer; and
forming first integrated pad-and-via bonding structures comprising a respective metallic via portion that is laterally surrounded by the first silicate glass layer and a respective metallic pad portion that is laterally surrounded by the first dielectric bonding material layer in the via cavities,
wherein one of the first integrated pad-and-via bonding structures comprises a first metallic barrier liner that contacts a sidewall of the first silicate glass layer, a horizontal surface of the first silicate glass layer, and an entire sidewall of the first dielectric bonding material layer.
382 teaches in Figs. 13,14 and 22 about a method of forming a semiconductor structure, comprising:
converting the via cavities (Fig. 13, item 81) into integrated pad-and-via cavities (Fig. 14, item 83) by performing a selective etch process that etches a material of the first dielectric bonding material layer selective to a material of the first silicate glass layer (“an anisotropic etch process to form first pad cavities 83. The first via-level dielectric layer 872 can be employed as an etch stop layer for the anisotropic etch process”, [0054], Ln. 9-11); and
forming first integrated pad-and-via bonding structures (Fig. 22, item 88) comprising a respective metallic via portion (Fig. 22, item 88V) that is laterally surrounded by the first silicate glass layer (Fig. 22, item 88V is surrounded by item 872) and a respective metallic pad portion (Fig. 22, item 88P) that is laterally surrounded by the first dielectric bonding material layer in the via cavities (Fig. 22, item 88P is surrounded by item 874),
wherein one of the first integrated pad-and-via bonding structures comprises a first metallic barrier liner (Fig. 22, combined items 82 and 84, “pad-and-via-level metallic liner”, [0091], Ln. 18-19) that contacts a sidewall of the first silicate glass layer, a horizontal surface of the first silicate glass layer, and an entire sidewall of the first dielectric bonding material layer (Fig. 22, combined items 82 and 84 contact a sidewall and a horizontal surface of item 872, and an entire sidewall of item 874 since item 84 is “an optional pad-and-via-level metallic seed layer”, [0091, Ln. 16-17]).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the selective etch process of the integrated pad-and-via cavities and the integrated pad-and-via bonding structure of 382 to vertically separate the pad interface from the first semiconductor devices (while providing electrical connectivity) in 562 as taught by 382 in at least Fig. 25.
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Fig. 22, annotated by Examiner from Okina, “382”
Regarding Claim 2. 382 teaches in Fig. 13 about a method of forming a semiconductor structure, comprising:
forming a hard mask layer including openings therethrough over the first dielectric bonding material layer (“a first photoresist layer (not shown) can be applied over the top surface of the first pad-level dielectric layer 874, and can be lithographically patterned to form via cavity shaped openings”, [0080], Ln. 1-4); and
performing an anisotropic etch process employing the hard mask layer as an etch mask to form the via cavities through the first dielectric bonding material layer and the first silicate glass layer (“an anisotropic etch process can be performed employing the patterned first photoresist layer as an etch mask layer. The pattern in the first photoresist layer can be transferred through the first pad-level dielectric layer 874 and the first via-level dielectric layer 872 to form first via cavities 81”, [0080], Ln. 4-9).
Regarding Claim 5. 382 teaches in Fig. 14 about a method of forming a semiconductor structure, wherein the selective etch process is performed while the hard mask layer is present on a top surf ace of the first dielectric bonding material layer (“photoresist layer (not shown) can be applied over the top surface of the first pad-level dielectric layer 874, and can be lithographically patterned to form pad cavity shaped openings which are wider than the via shaped openings” [0082], Ln. 2-6).
Regarding Claim 6. 382 teaches in Fig. 14 about a method of forming a semiconductor structure, wherein a thickness of the first dielectric bonding material layer remains unchanged during the selective etch process (thickness of layer 874 does not change since “photoresist layer (not shown) can be applied over the top surface of the first pad-level dielectric layer 874” [0082], Ln. 3-4).
Regarding Claim 8. 382 teaches in Fig. 22 about a method of forming a semiconductor structure, wherein:
the first dielectric bonding material layer comprises a first silicon carbide nitride layer (“dielectric layer 874 includes … silicon carbide nitride”, [0067], Ln. 24-25); and
the first metallic barrier liner comprises an electrically conductive metal nitride or an electrically conductive metal carbide layer (“pad-and-via-level metallic liners 82 comprise, and/or consist of, a metallic nitride material”, [0088], Ln. 11-13) which extends from a bottom surface to a top surface of the first silicon carbide nitride layer (grouped items 82 and 84 extend from a bottom surface to a top surface of the layer item 874) and which surrounds a metal or metal alloy fill material portion (item 86 “pad-and-via level metallic fill portion” [0091], Ln. 17-18, is surrounded by grouped liner items 82 and 84).
Regarding Claim 9. 562 teaches in Fig. 10A about a method of forming a semiconductor structure, comprising:
providing a second semiconductor die (item 700) including second dielectric material layers (item 760) located on second semiconductor devices (item 720, wherein item 760 is located on the bottom of item 720) and embedding second metal interconnect structures (item 780), and further including a second bonding-level dielectric layer (items 762 and 790) embedding metallic bonding structures (item 798); and
bonding the metallic bonding structures to the first integrated pad-and-via bonding structures by metal-to-metal bonding (“first metallic bonding pad 998 and a second metallic bonding pad 798 to provide metal-to-metal bonding”, [0083], Ln. 6-8).
Regarding Claim 10. 562 teaches in Fig. 10A about a method of forming a semiconductor structure, comprising:
further comprising bonding the second bonding-level dielectric layer to the first dielectric bonding material layer by dielectric-to-dielectric bonding (“the first semiconductor die 900 and the second semiconductor die 700 can be bonded to each other by wafer-to-wafer bonding”, [0074], Ln. 1-3).
Allowable Subject Matter
Claims 3-4 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art does not teach or suggest the claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897
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