DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a FINAL OFFICE ACTION in response to the Amendment/ Remarks filed 01/20/2026. Claims 6 and 16 have been cancelled.
Claims 1-5, 7-15 and 17-22 are pending in the Application, of which Claims 1, 11 and 20 are independent.
Continuity/Priority information
The present Application 18509019 filed 11/14/2023 claims foreign priority to CHINA, Application No. 202310804980.X, filed 06/30/2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/12/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Response to Arguments
Applicant's arguments, see Amendment/ Remarks filed 01/20/2026 with respect to the rejection of Claims 1-5, 7-15 and 17-22 under 35 U.S.C. 102(a)(1) as being anticipated by Maffeis (Pub. No. US 20170269995), have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of Micheloni et al. (U.S. Patent No. 8,621,318) Pub. Date: 2013-12-31, as set forth in the present office action.
With respect to the rejection of Claims under 35 U.S.C. 102(a)(1), Applicant argues that in the Maffeis reference, the redundant way of encoding the information bits is utilized prior to hard and/or soft decoding, while the instant Application describes a memory system where a read retry operation and a soft decode operation (e.g., the first-type read error processing flow) is performed at least twice before a RAID operation (e.g., the second-type read error processing flow). Accordingly, Maffeis does not teach the memory system where the first-type read error processing flow is performed at least twice prior to the performance of the second-type read error processing flow.
In response to Applicant arguments, under a new ground(s) of rejection, Micheloni illustrates in FIG. 3 a flow of encoded data having an outer BCH code concatenated with an inner LDPC code. If the nonvolatile memory system fails to recover the data 305, the nonvolatile memory system will communicate the read request to a redundant array of independent disks (RAID) module 345 to recover the data 305. A RAID algorithm may be performed by the RAID control module 345 on a standard RAID level (e.g., a RAID level 3-6), as is known in the relevant art.
As illustrated in Fig. 3, in Micheloni, the hard-decision LDPC decoder 335 operation followed by the soft-decision LDPC decoder 340 operation, i.e. “first-type read error processing flow” is performed prior to the RAID operation, i.e. “second -type read error processing flow”.
With respect to “the operation is performed at least twice”, Micheloni discloses various methods for decoding data encoded with LDPC error correction codes are known in the art. Two general LDPC decoding methods known in the art are soft-decision decoding and hard-decision decoding. Soft-decision decoding algorithms, such as the sum-product algorithm (SPA) and min-sum algorithm (MSA) are iterative and are based on belief propagation.
Clearly, since both hard and soft decoding procedures are iterative, as it is well known in the art they both perform repetitive sequence of operations multiple times.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-15 and 17-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Micheloni et al. (U.S. Patent No. 8,621,318) Pub. Date: 2013-12-31.
Regarding independent Claims 1, 11 and 20, Micheloni discloses Nonvolatile Memory Controller With Error Detection, comprising:
a memory controller coupled to the memory device, FIG. 1 illustrates a nonvolatile memory system 105 that includes a nonvolatile memory controller 110 and a nonvolatile memory storage module 115 coupled to the nonvolatile memory controller 110. The nonvolatile memory system 105 may be a solid stated drive (SSD).
configured to perform a read operation on a memory region; FIG. 3, upon receiving a read request at the nonvolatile memory system 300, the nonvolatile memory system 300 reads the encoded data from the nonvolatile memory storage module 330 and communicates the encoded data, including the data 305 and the LDPC code 310, to the hard-decision LDPC decoder 335.
in response to a failure of the read operation, perform a first-type read error and a second-type read error processing flow in sequence, wherein the first-type read error includes at least one of a read retry operation and a soft decode operation, and the first-type read error is performed at least twice prior to a performance of the second-type read error processing flow;
As illustrated in Fig. 3, the hard-decision LDPC decoder 335 operation followed by the soft-decision LDPC decoder 340 operation, i.e. “first-type read error processing flow” is performed prior to the RAID operation, i.e. “second -type read error processing flow”.
With respect to “the operation is performed at least twice”, Micheloni discloses two general LDPC decoding methods known in the art are soft-decision decoding and hard-decision decoding. Soft-decision decoding algorithms, such as the sum-product algorithm (SPA) and min-sum algorithm (MSA) are iterative and are based on belief propagation. Clearly, since both hard and soft decoding procedures are iterative, as it is well known in the art they both perform repetitive sequence of operations multiple times.
wherein the second- type read error includes a redundant array independent disk (RAID) operation, and wherein the read retry, the soft decode, and the RAID are error correction operations; Fig. 3, If the nonvolatile memory system fails to recover the data 305 from the encoded data using the soft-decision LDPC decoder 340 followed by the BCH decoder 337, the nonvolatile memory system will communicate the read request to a redundant array of independent disks (RAID) module 345 to recover the data 305. A RAID algorithm may be performed by the RAID control module 345 on a standard RAID level (e.g., a RAID level 3-6), as is known in the relevant art.
and in response, send the failure of the read operation to a host.
If there aren't any decoding errors resulting from decoding the concatenation encoded data using the hard-decision inner error correction code 415, the data may be recovered without being corrected by the outer error correction code and the nonvolatile memory controller may transfer the recovered data to a host processor.
Regarding Claims 2, 12, Micheloni discloses wherein an average processing time of the first-type read error processing flow is less than the second-type read error processing flow.
FIG. 4, After the concatenation encoded data is read from the nonvolatile memory storage module 405, the nonvolatile memory controller may recover the data from the concatenation encoded data by decoding the concatenation encoded data using the inner error correction code with a hard-decision algorithm 410 “first-type read error”.
FIG. 4, To recover the data from the concatenation encoded data, the nonvolatile memory storage module may decode the data using the inner error correction code with a soft-decision algorithm 430 “first-type read error” and then determine if there are any errors resulting from the decoding of the concatenation encoded data using the inner error correction code 435.
FIG. 4, When the outer error correction code is unable to successfully recover the data from the concatenation encoded data using the outer error correction code, the nonvolatile memory controller may attempt to recover the data from the concatenated encoded data using a redundant array of independent disks (RAID) operation 450 “second-type read error” may be performed to recover the data.
Regarding Claims 4, 5, 7, 14, 15, 17, Micheloni discloses a first-type read error and a second-type read error which are performed in sequence; Fig. 4, hard-decision algorithm 410 and soft-decision algorithm 430 corresponding to “first-type read error” and redundant array of independent disks (RAID) operation 450 corresponding to “second-type read error”.
Regarding Claims 8, 9, 10, 18, 19, Micheloni discloses determine a number of executions of the first-type read error processing flow based on the first duration. FIG. 4 illustrates a flow diagram 400 for a method of recovering encoded data in a nonvolatile memory controller in accordance with an embodiment of the present invention. In accordance with various embodiments, upon receiving a read request for data stored in a nonvolatile memory storage module, the nonvolatile memory controller initiates a request to read the concatenation encoded data stored in the nonvolatile memory storage module 405.
Regarding Claims 3, 13, 21, 22, Micheloni discloses wherein the memory region is restored to the operating state when at least one of an operation of the memory region can be performed. If the encoded data was not successfully decoded by the hard-decision inner error correction code decoding and the outer error correction code decoding and if the encoded data was not successfully decoded by the soft-decision inner error correction code decoding and the outer error correction code decoding, the nonvolatile memory may recover the data by performing a redundant array of independent disks (RAID) operation of the encoded data.
If the number of errors resulting from decoding the concatenation encoded data using the soft-decision inner error correction code does not exceed the correction capacity of the outer error correction code, the data errors may be corrected using the outer error correction code 445 to successfully recover the data from the concatenated encoded data and the nonvolatile memory controller may transfer the recovered data to a host processor.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: February 10, 2026
Final Rejection 20260210
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV