Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II, claims 15-20 in the reply filed on 04/20/2026 is acknowledged.
Claim 1-14 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention I, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/20/2026
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by United States Patent Application Publication by Yoshida (US 20220254804 A1)
Regarding claim 15, Yoshida discloses a semiconductor device, comprising:
a stack structure (Fig. 19A, where alternating layers 232L, 242L, 132L, and 142L make up a stack structure), wherein the stack structure comprises dielectric layers (132L, 232L) and gate line layers (146, 246) stacked alternately, and the stack structure comprises first regions (All areas not on C-C’ cross section in Fig. 19B) and second regions (All area on C-C’ cross section in Fig. 19B);
channel structures (58) that are located in the first regions (Fig. 25, there are many channel structures 58 around the device including in the first region(s)) and penetrate through the stack structure along a first direction (Fig. 12A-D, we will call the first direction to be into the device through the stack structure and into the substrate, typically considered the Z-direction); and
gate line isolation structures (176) that are located in the second regions and extend along a second direction (Fig. 18A, where gate line isolation structures are located on the C-C’ cross section and the second direction will be considered the same as the C-C’ line), the gate line isolation structures penetrating through the stack structure along the first direction (Para. 156, “The dielectric fin portions 176F may be formed by filling the backside recesses (i.e., air gaps) (142, 242) with the dielectric material of the continuous dielectric wall structures 176), and the gate line isolation structures being in a concavo-convex shape along a third direction, wherein the second direction intersects the first direction, and the third direction intersects the first direction and the second direction (Third direction will be hd2).
Regarding claim 16, Yoshida discloses the semiconductor device of claim 15, further comprising a protective layer (153) disposed on a top of the stack structure (Fig. 13D, where protective layer 153 is on top of stack structure).
Regarding claim 17, Yoshida discloses the semiconductor device of claim 15, and further wherein the gate line isolation structures comprise sidewalls extending along the second direction, the sidewalls comprise a plurality of substructures connected end to end, and two adjacent ones of the plurality of substructures are not coplanar (Fig. 18B, where sidewalls of the gate line isolation structures 176 extend along the second direction [hd1], the sidewalls comprise a plurality of sub structures connected end to end, and any two substructures are not coplanar).
Regarding claim 18, Yoshida discloses the semiconductor device of claim 15, and further wherein the stack structure comprises a core area (100) and a stair step area (200), and sizes of the gate line isolation structures located in the core area along the third direction are equal to the sizes of the gate line isolation structures located in the stair step area along the third direction (In the reference the gate line isolation structures located both inside the core area and the stair step area is the same structure made the same way).
Claims 15, 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by United States Patent Application Publication by Fukuzumi et al. (US 20220068317 A1; Fukuzumi)
Regarding claim 15, Fukuzumi discloses a semiconductor device, comprising:
a stack structure (32), wherein the stack structure comprises dielectric layers (36) and gate line layers (92) stacked alternately, and the stack structure comprises first regions (12, 14) and second regions (16);
channel structures (51) that are located in the first regions and penetrate through the stack structure along a first direction (First direction being the Z-direction) (Fig. 7B, Where Channel structure extends in the third direction); and
gate line isolation structures (48, 50, 52) that are located in the second regions and extend along a second direction (Fig. 7, where gate isolation structures extend in the y direction which we will call the second direction), the gate line isolation structures penetrating through the stack structure along the first direction (Fig. 7a, where isolation structures penetrate through the stack structure in the first direction), and the gate line isolation structures being in a concavo-convex shape along a third direction, wherein the second direction intersects the first direction, and the third direction intersects the first direction and the second direction (Fig. 6, where along the X direction which we will call the third direction, the gate line isolation structures appear to be in a concavo-convex shape) .
Regarding claim 19, Fukuzumi discloses the semiconductor device of claim 15, wherein the stack structure comprises a core area (22) and a stair step area (72, 74), and sizes of the gate line isolation structures located in the core area along the third direction are smaller than the sizes of the gate line isolation structures located in the stair step area along the third direction (Figs. 11-13 shows the gate line isolation structures being a different size along the third direction).
Regarding claim 20, Fukuzumi discloses a memory system, comprising a controller and a three-dimensional memory, wherein the controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory to store data, and the three-dimensional memory comprises a semiconductor device comprising (Para. 5, where a memory system with a controller is discussed):
a stack structure (32), wherein the stack structure comprises dielectric layers (36) and gate line layers (92) stacked alternately, and the stack structure comprises first regions (12, 14) and second regions (16);
channel structures (51) that are located in the first regions and penetrate through the stack structure along a first direction (First direction being the Z-direction) (Fig. 7B, Where Channel structure extends in the third direction); and
gate line isolation structures (48, 50, 52) that are located in the second regions and extend along a second direction (Fig. 7, where gate isolation structures extend in the y direction which we will call the second direction), the gate line isolation structures penetrating through the stack structure along the first direction (Fig. 7a, where isolation structures penetrate through the stack structure in the first direction), and the gate line isolation structures being in a concavo-convex shape along a third direction, wherein the second direction intersects the first direction, and the third direction intersects the first direction and the second direction (Fig. 6, where along the X direction which we will call the third direction, the gate line isolation structures appear to be in a concavo-convex shape) .
Conclusion
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/DANIEL J HIBBERT/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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