Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 23rd, 2026 has been entered.
Response to Arguments
2. Applicant’s arguments, filed February 23rd, 2026, with respect to the rejections of the independent claims under 35 U.S.C. 102 have been fully considered and are persuasive in light of the claim amendments. Therefore, the rejections have been withdrawn. However, upon further consideration, new grounds of rejection are made in view of Prener (US 5,125,092).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-3, 5-9, and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Plotnikov et al (US 2019/0347104, herein Plotnikov) in view of Prener (US 5,125,092).
Regarding claim 1, Plotnikov teaches a circuit, comprising:
a first register to maintain values at first ordered positions of the first register ([0003], vector registers, [0059-0060], ordered bit positions);
a second register to maintain values at second ordered positions of the second register ([0003], [0059-0060], vector registers with ordered bit positions);
circuitry to perform an all-to-all comparison between the values maintained at the first ordered positions of the first register and the values maintained at the second ordered positions of the second register ([0040], [0060], [0068], all-to-all comparison instructions of input vector elements); and
a matrix tile comprising an array of storage cells to store results of the all-to-all comparison ([0037], result vector), wherein individual storage cells of the array of storage cells respectively comprise a plurality of bits configured to encode one of at least three comparison outcomes for an associated comparison of the all-to-all comparison wherein the at least three comparison outcomes comprise a less than condition, an equal to condition, or a greater than condition ([0005], [0040], greater, lesser, or equal comparison operation results).
Plotnikov fails to teach wherein the storage cells comprise a plurality of bits configured to encode the less than condition, equal to condition, and greater than condition.
Prener teaches a circuit configured to perform a comparison operation wherein storage cells comprise a plurality of bits configured to encode an outcome of the comparison operation comprising a less than condition, equal to condition, and greater than condition (4:62-64, use three bits to encode possible outcomes of a comparison as greater, less, or equal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Plotnikov and Prener to utilize a single encoding scheme for multiple comparison outcomes. While Plotnikov teaches the output of the all-to-all comparison operation as resulting in a single bit outcome indicating one of the three possible outcome states, one of ordinary skill in the art would understand that by combining all three outcomes into a single bit field using three bits would allow the processor to store additional results in a single output element. While this would increase the bit size of the results, this is a commonplace tradeoff in the microprocessor art, wherein increasing bit overhead and complexity allows for increased performance and efficiency. As both Plotnikov and Prener disclose the use of comparison operations that result in one of three outcomes, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 2, The combination of Plotnikov and Prener teaches the circuit of claim 1, wherein the matrix tile further comprises the circuitry to perform the all-to-all comparison, and wherein the circuitry to perform the all-to-all comparison comprises a two-dimensional array of circuitry to perform comparison operations of the all-to-all comparison (Plotnikov [0005], [0037-0040], greater, lesser, or equal comparison operations, [0057], [0073], execution circuits).
Regarding claim 3, The combination of Plotnikov and Prener teaches the circuit of claim 1, wherein the individual storage cells respectively comprise three bits to encode the one of the at least three comparison outcomes (Plotnikov [0005], [0037-0040], greater, lesser, or equal comparison operations & Prener 4:62-64, use three bits to encode possible outcomes of a comparison as greater, less, or equal).
Regarding claim 5, The combination of Plotnikov and Prener teaches the circuit of claim 1, comprising a processor including: an instruction decoder to decode instructions, wherein the processor, including the first register and the second register and further including the circuitry to perform the all-to-all comparison between the values maintained at the first ordered positions of the first register and the values maintained at the second ordered positions of the second register, is configured to perform data processing in response to instructions decoded by the instruction decoder; wherein the instruction decoder is configured to control, at least in part, the circuitry to perform the all-to-all comparison between the values maintained at the first ordered positions of the first register and the values maintained at the second ordered positions of the second register (Plotnikov [0057], [0059], instruction decoder to decode instructions & control execution, [0060], execution units for performing all-to-all comparisons).
Regarding claim 6, The combination of Plotnikov and Prener teaches the circuit of claim 5, wherein the processor further comprises the matrix tile comprising the array of storage cells to store the results of the all-to-all comparison ([0040], [0068], matrices used to store input and outputs), wherein the matrix tile further comprises the circuitry to perform the all-to-all comparison, and wherein the circuitry to perform the all-to-all comparison comprises a two-dimensional array of circuitry to perform comparison operations of the all-to-all comparison ([0005], [0037-0040], greater, lesser, or equal comparison operations, [0057], [0073], execution circuits).
Claims 7-9 and 11-12 refer to a method embodiment of the circuit embodiment of claims 1-3 and 5-6, respectively. Therefore, the above rejections for claims 1-3 and 5-6 are applicable to claims 7-9 and 11-12, respectively.
Claim 13 refers to an article embodiment of the circuit embodiment of claim 1. Therefore, the above rejection for claim 1 is applicable to claim 13.
Regarding claim 14, The combination of Plotnikov and Prener teaches the article of claim 13, wherein the matrix tile further comprises a two-dimensional array of circuitry to perform comparison operations of the all-to-all comparison ([0005], [0037-0040], greater, lesser, or equal comparison operations, [0057], [0073], execution circuits), wherein the processing device further to perform a merge operation, a merge-sort operation, and/or an intersect operation based at least in part on the results of the all-to-all comparison ([0090], merging, zeroing, or other manipulation of vector operation results).
4. Claims 4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Plotnikov and Prener in view of Mimar (US 2013/0212355).
Regarding claim 4, The combination of Plotnikov and Prener teaches the circuit of claim 1, wherein the individual storage cells respectively comprise a plurality of bits, wherein the bits represent an equal to result, a greater than result, or a less than result ([0005], [0040], greater, lesser, or equal comparison operation results).
Plotnikov and Prener fail to teach the bits comprising four bits N, Z, C, and V which indicate the results.
Mimar teaches a circuit for performing vector operations wherein a plurality of bits comprise four bits N, Z, C, and V, wherein bit Z represents an equal to result, (N==Z)&&(Z==0) encodes a greater than result, and !(N==Z) encodes a less than result (Mimar [0024], Table 1, use of N, Z, C, and V condition code bits to indicate equal, greater than, or less than results).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Plotnikov, Prener, and Mimar to utilize the condition code bit mappings for indicating comparison results. While Plotnikov does not disclose the use of condition code bits, both Plotnikov and Mimar disclose the use of comparison operations for influencing the operation of additional vector instructions dependent upon those results. Modifying the three bits disclosed by Prener to instead utilize the microprocessor-standard condition code bits would allow for the processor to use already existing bit fields for the comparison results. Therefore, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and would have been obvious to one of ordinary skill in the art.
Claim 10 refers to a method embodiment of the circuit embodiment of claim 4. Therefore, the above rejection for claim 4 is applicable to claim 10.
5. Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Plotnikov and Prener in view of Smelyanskiy et al (US 2009/0249026, herein Smelyanskiy).
Regarding claim 15, The combination of Plotnikov and Prener teaches a circuit, comprising:
a matrix tile comprising an array of storage cells to store results of an all-to-all comparison between values maintained at first ordered positions of a first register and values maintained at second ordered positions of a second register ([0003], [0059-0060], [0068], performing all-to-all comparison on ordered positions of vectors in vector register), wherein individual storage cells of the array of storage cells respectively comprise a plurality of bits to indicate whether an associated comparison of the all-to-all comparison resulted in a less than condition, an equal to condition, or a greater than condition ([0005], [0040], greater, lesser, or equal comparison operation results);
circuitry to hold comparison results for individual rows or columns of the matrix tile ([0037], [0048], store results of comparisons); and
circuitry to load the comparison results for the individual rows or columns of the matrix tile into respective positions of third ordered positions of a third register ([0059], store result in destination vector register).
Plotnikov fails to teach wherein the storage cells comprise a plurality of bits configured to encode the less than condition, equal to condition, and greater than condition.
Prener teaches a circuit configured to perform a comparison operation wherein storage cells comprise a plurality of bits configured to encode an outcome of the comparison operation comprising a less than condition, equal to condition, and greater than condition (4:62-64, use three bits to encode possible outcomes of a comparison as greater, less, or equal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Plotnikov and Prener to utilize a single encoding scheme for multiple comparison outcomes. While Plotnikov teaches the output of the all-to-all comparison operation as resulting in a single bit outcome indicating one of the three possible outcome states, one of ordinary skill in the art would understand that by combining all three outcomes into a single bit field using three bits would allow the processor to store additional results in a single output element. While this would increase the bit size of the results, this is a commonplace tradeoff in the microprocessor art, wherein increasing bit overhead and complexity allows for increased performance and efficiency. As both Plotnikov and Prener disclose the use of comparison operations that result in one of three outcomes, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Plotnikov and Prener fail to teach the circuitry accumulating the comparison results.
Smelyanskiy teaches a circuit for performing comparison on vector data and accumulating the comparison results ([0044], [0048], accumulating results of comparison operations).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Plotnikov and Prener with those of Smelyanskiy to utilize an accumulation operation for combining comparison results. While Plotnikov does not disclose the use of accumulation operations, both Plotnikov and Smelyanskiy disclose the use of comparison operations for influencing the operation of additional vector instructions dependent upon those results, and Plotnikov does teach the use of merge operations for merging vector operation results. Therefore, utilizing an accumulation operation would merely entail a simple substitution of known prior art elements to achieve predictable results, and would have been obvious to one of ordinary skill in the art.
Regarding claim 16, the combination of Plotnikov, Prener, and Smelyanski teaches the circuit of claim 15, wherein the matrix tile further comprises a two-dimensional array of circuitry to perform comparison operations of the all-to-all comparison (Plotnikov [0005], [0037-0040], greater, lesser, or equal comparison operations, [0057], [0073], execution circuits).
Regarding claim 17, the combination of Plotnikov, Prener, and Smelyanski teaches the circuit of claim 15, wherein the array of storage cells respectively comprise three bits to indicate the less than result, the equal to result, or the greater than result for an associated comparison resulting from the all-to-all comparison (Plotnikov [0005], [0040], greater, lesser, or equal comparison operation results).
Claims 18 and 19 refer to a method embodiment of the circuit embodiment of claims 15 and 16, respectively. Therefore, the above rejections for claims 15 and 16 are applicable to claims 18 and 19, respectively.
6. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Plotnikov, Prener, and Smelyanski in view of Mimar.
Regarding claim 20, the combination of Plotnikov, Prener, and Smelyanski teaches the method of claim 18, wherein the individual storage cells respectively comprise a plurality of bits (Plotnikov [0005], [0040], greater, lesser, or equal comparison operation results).
Plotnikov, Prener, and Smelyanski fail to teach the bits comprising four bits N, Z, C, and V which indicate the results.
Mimar teaches a circuit for performing vector operations wherein a plurality of bits comprise four bits N, Z, C, and V, wherein bit Z represents an equal to result, (N==Z)&&(Z==0) indicates a greater than result, and !(N==Z) indicates a less than result (Mimar [0024], Table 1, use of N, Z, C, and V condition code bits to indicate equal, greater than, or less than results).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Plotnikov, Prener, and Smelyanski with those of Mimar to utilize the condition code bit mappings for indicating comparison results. While Plotnikov does not disclose the use of condition code bits, both Plotnikov and Mimar disclose the use of comparison operations for influencing the operation of additional vector instructions dependent upon those results. Therefore, utilizing a standardized bit scheme for controlling vector instruction execution would merely entail a simple substitution of known prior art elements to achieve predictable results, and would have been obvious to one of ordinary skill in the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sijstermans (US 6,904,510) discloses a processor that performs comparison operations with three possible results.
Matsuo (US 2003/0061471) discloses a processor wherein flag bits encode a less than, equal to, or greater than comparison outcome.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183