Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/14/2026 has been entered.
Claim Objections
Claim 12 is objected to because of the following informalities:
Claim 12 recites the limitation “a first electrode” and “a second electrode" in line 2. It is unclear whether “a first electrode” and “a second electrode" was intended to relate back to “the first electrode” and “the second electrode" in claim 1.
For purpose of compact prosecution, “a first electrode” and “a second electrode" will be treated as if it were “the first electrode” and “the second electrode," respectively.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the first electrode” and “the second electrode" in lines 10-11. There is insufficient antecedent basis for this limitation in the claim.
For purpose of compact prosecution, “the first electrode” and “the second electrode" will be treated as if it were “a first electrode” and “a second electrode," respectively.
Claims 2-3, 5-13, and 16 are rejected as they were dependent on rejected claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-6, 9-13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over HAN et al. (U.S. 2021/0118944 A1, hereinafter refer to HAN) in view of Chong (U.S. 2024/0332476 A1, hereinafter refer to Chong) and Wu et al. (U.S. 2018/0277591 A1, hereinafter refer to Wu).
Regarding Claim 1: HAN discloses a vertical-type light-emitting diode (see HAN, Fig.12 as shown below and ¶ [0002]), comprising:
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a substrate (210) (see HAN, Fig.12 as shown above);
a semiconductor stack layer (243/244/245) disposed on the substrate (210), wherein the semiconductor stack layer (243/244/245) comprises a first semiconductor layer (243), a light-emitting layer (244) and a second semiconductor layer (245) that are sequentially stacked on the substrate (210);
an insulation implant layer (242) formed in the semiconductor stack layer (243/244/245) to divide the semiconductor stack layer (243/244/245) into at least two individual dies (240) (see HAN, Fig.12 as shown above and ¶ [0084]).
HAN is silent upon explicitly disclosing wherein a material of the insulation implant layer comprises hydrogen atoms or helium atoms.
For support see Chong, which teaches wherein a material of the insulation implant layer (190) comprises hydrogen atoms or helium atoms (see Chong, Fig.2b as shown below, ¶ [0021], ¶ [0035], and ¶ [0126]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of HAN and Chong to enable the HAN’s isolation implant layer to comprises hydrogen atoms or helium atoms as taught by Chong in order to isolates the LED units corresponding to the adjacent LED units, and divides the LED semiconductor layer into the plurality of LED units arranged in an array.
The combination of HAN and Chong is silent upon explicitly disclosing wherein the first semiconductor layer is an N-type semiconductor layer, the second semiconductor layer is a P-type semiconductor layer, the first electrode is a common cathode electrode, and the second electrode is a common anode electrode.
For support see Wu, which teaches wherein the first semiconductor layer (116) is an N-type semiconductor layer, the second semiconductor layer (112) is a P-type semiconductor layer, the first electrode (220 and 130) is a common cathode electrode, and the second electrode (120 and 240) is a common anode electrode (see Wu, Fig.3 as shown below, ¶ [0004]- ¶ [0005], ¶ [0030], ¶ [0032], ¶ [0036], and ¶ [0039]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of HAN, Chong, and Wu to enable the HAN semiconductor stack layer to include an N-type first semiconductor layer, a P-type second semiconductor layer, common first electrode, and common second electrode as taught by Wu in order to obtain a display panel which is capable of a favorable cooling effect, a favorable electrical characteristic and a favorable production yield rate.
Regarding Claim 2: HAN as modified teaches a vertical-type light-emitting diode as set forth in claim 1 as above. The combination of HAN, Chong, and Wu further teaches wherein the insulation implant layer (242) extends downwardly from an upper surface of the second semiconductor layer (245) into the first semiconductor layer (243) (see HAN, Fig.12 as shown above and ¶ [0084]).
Regarding Claim 3: HAN as modified teaches a vertical-type light-emitting diode as set forth in claim 1 as above. The combination of HAN, Chong, and Wu further teaches wherein the insulation implant layer (242) is directly formed in the semiconductor stack layer (243/244/245) by means of ion implantation (see HAN, Fig.12 as shown above and ¶ [0084]).
Note: patentability of a product does not depend on its method of production.
Regarding Claim 5: HAN as modified teaches a vertical-type light-emitting diode as set forth in claim 1 as above. The combination of HAN, Chong, and Wu further teaches wherein the at least two individual dies (240) are insulated from each other (see HAN, Fig.12 as shown above).
Regarding Claim 6: HAN as modified teaches a vertical-type light-emitting diode as set forth in claim 1 as above. The combination of HAN, Chong, and Wu further teaches wherein each of the individual dies (240) comprises the first semiconductor layer (243), the light-emitting layer (244) and the second semiconductor layer (245) stacked in sequence (see HAN, Fig.12 as shown above).
Regarding Claim 9: HAN as modified teaches a vertical-type light-emitting diode as set forth in claim 1 as above. The combination of HAN, Chong, and Wu further teaches wherein a thickness of the insulation implant layer (242, note: the thickness of 242 is equal to the thickness of 240) ranges from 1.5 μm to 2 μm (less than or equal to approximately 7 μm) (see HAN, Fig.12 as shown above and ¶ [0127]).
Regarding Claim 10: HAN as modified teaches a vertical-type light-emitting diode as set forth in claim 1 as above. The combination of HAN, Chong, and Wu further teaches wherein a thickness of the semiconductor stack layer (243/244/245) is less than or equal to 2 μm (less than or equal to approximately 7 μm) (see HAN, Fig.12 as shown above and ¶ [0127]).
Regarding Claim 11: HAN as modified teaches a vertical-type light-emitting diode as set forth in claim 1 as above. The combination of HAN, Chong, and Wu further teaches wherein a height difference of an upper surface of the vertical-type light-emitting diode is less than 0.5 μm (note: no height difference between individual vertical-type light-emitting diode, which is considered equivalent to the claimed invention limitation) (see HAN, Fig.12 as shown above).
Regarding Claim 12: HAN as modified teaches a vertical-type light-emitting diode as set forth in claim 1 as above. The combination of HAN, Chong, and Wu further teaches wherein the vertical-type light-emitting diode further comprises a first electrode (130/220) and a second electrode (120/240), the first electrode (130/220) is disposed between the semiconductor stack layer (110) and the substrate (210), and the second electrode (120/240) is disposed on one side of the semiconductor stack layer (110) away from the substrate (210), wherein the at least two individual dies (110) share the first electrode (130/220) and the second electrode (120/240) to form a parallel connection structure (see Wu, Fig.3 as shown above).
Regarding Claim 13: HAN as modified teaches a vertical-type light-emitting diode as set forth in claim 12 as above. The combination of HAN, Chong, and Wu further teaches wherein the second electrode (120/240) adopts a transparent current spreading electrode and/or a metal electrode (see Wu, Fig.3 as shown above and ¶ [0030]).
Regarding Claim 16: HAN as modified teaches a vertical-type light-emitting diode as applied to claim 1 above. The combination of HAN, Chong, and Wu further teaches a light-emitting device, comprising: a circuit substrate (230) and a vertical-type light-emitting diode (240) (see HAN, Fig.12 as shown above),
wherein the vertical-type light-emitting diode (240) is disposed on the circuit substrate (230), and the vertical-type light-emitting diode (240) adopts the vertical-type light-emitting diode according to claim 1 (see HAN, Fig.12 as shown above).
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over HAN et al. (U.S. 2021/0118944 A1, hereinafter refer to HAN), Chong (U.S. 2024/0332476 A1, hereinafter refer to Chong), and Wu et al. (U.S. 2018/0277591 A1, hereinafter refer to Wu) as applied to claim 1 above, and further in view of Applicant Admitted Prior Art (U.S. 2024/0170609 A1, hereinafter refer to AAPA).
Regarding Claim 7: HAN as modified teaches a vertical-type light-emitting diode as applied to claim 1 above. The combination of HAN, Chong, and Wu is silent upon explicitly disclosing wherein a spacing between two of the adjacent insulation implant layers is less than or equal to 5 μm.
For support see AAPA, which teaches wherein a spacing between two of the adjacent insulation implant layers (PI) is less than or equal to 5 μm (see AAPA, Fig.1F as shown below and ¶ [0005]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of HAN, Chong, Wu, and AAPA to enable the spacing between two of the adjacent insulation implant layers of HAN to be within the recited ranges as taught by AAPA in order to obtain a very small chip size.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over HAN et al. (U.S. 2021/0118944 A1, hereinafter refer to HAN), Chong (U.S. 2024/0332476 A1, hereinafter refer to Chong), and Wu et al. (U.S. 2018/0277591 A1, hereinafter refer to Wu) as applied to claim 1 above, and further in view of Xia (CN 109004078 B, hereinafter refer to Xia).
Regarding Claim 8: HAN as modified teaches a vertical-type light-emitting diode as applied to claim 1 above. The combination of HAN, Chong, and Wu is silent upon explicitly disclosing wherein a width of the insulation implant layer is less than or equal to 2 μm.
For support see Xia, which teaches wherein a width (d) of the insulation implant layer (M) is less than or equal to 2 μm (the width of groove K adjacent between two micro-LED1011 is d, wherein 1μm ≤ d is less than or equal to 5μm) (see Xia, Figs.3, 5, and 8 and page.5).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of HAN, Chong, Wu, and Xia to enable the Han insulation implant layer to have the recited width as taught by Xia in order to reduce the lateral light leakage of the micro LED and improving the display effect.
Conclusion
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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