Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 6-19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 4, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20190229160 A1) hereafter referred to as Lee in view of Shin et al. (US 20180190204 A1) hereafter referred to as Shin
In regard to claim 1 Lee teaches [“FIG. 1 is a plan view illustrating a display device according to exemplary embodiments of the present disclosure”] a display apparatus comprising:
a substrate [“Referring to FIGS. 1 and 2, the display device may include a substrate SUB” “substrate SUB may include a display area DA and a non-display area disposed on at least one side of the display area DA”] having a display area and a peripheral area outside the display area;
a transistor in the display area [“Each of the pixels PXL may be a light emitting element including an organic light emitting layer” “Referring to FIGS. 3 and 4, the pixels PXL may include a light emitting element OLED, first to seventh transistors T1 to T7, and a storage capacitor Cst”] and a light-emitting element electrically connected to the transistor; and
a scan driver [“In. FIG. 3, the positions of the scan driver SDV, the emission driver EDV the data driver DDV, and the timing controller TC are shown in one possible configuration”, see that the SDV is outside the DA ] in the peripheral area,
but does not state wherein the scan driver comprises:
a first transistor disposed on the substrate and comprising a first semiconductor layer comprising an oxide semiconductor and a first gate electrode overlapping the first semiconductor layer;
a second transistor disposed on the substrate and comprising a second semiconductor layer comprising a silicon semiconductor and a second gate electrode overlapping the second semiconductor layer; and
insulating layers disposed on the substrate and defining dummy holes not overlapping the first semiconductor layer and the second semiconductor layer, wherein the dummy holes are spaced apart from the first semiconductor layer and the second semiconductor layer and overlap dummy semiconductor layers adjacent to the first semiconductor layer.
See Lee teaches “In the non-display area NDA, the wiring portion LP disposed in the fan-out area FTA may be formed” “The dummy active pattern DACT may be disposed in the second area II of the fan-out area FTA” “The dummy active pattern DACT may be a semiconductor pattern including polysilicon, amorphous silicon, oxide semiconductor, or the like. In some exemplary embodiments of the present disclosure, the dummy active pattern DACT may include the same material as the first to seventh active patterns ACT1 to ACT7 and may be disposed on the same layer as the first to seventh active patterns ACT1 to ACT7” “Since a separate photoresist pattern is added to the non-display area NDA to form the first and second dummy lines DFL1 and DFL2 and the dummy active pattern DACT in the fan-out area FTA, the density of the photoresist pattern in the non-display area NDA may be increased. Thus, the density of the photoresist pattern in the non-display area NDA may be made similar to the density of the photoresist pattern in the display area DA” see basic transistor layour “One end of the first connecting line CNL1 may be connected to the first gate electrode GE1 through a first contact hole CH1 and the other end of the first connecting line CNL1 may be connected to the third drain electrode DE3 and the fourth drain electrode DE4 through a second contact hole CH2”.
See Shin teaches “A scan driver, includes a plurality of stage circuits, each of which includes a driving circuit unit providing an output signal and an inverter inverting the output signal of the driving circuit unit and generating a scan signal, in which the inverter includes a first transistor and a second transistor, which are complementarily operated, the first transistor is a P-type polysilicon transistor, and the second transistor is an N-type oxide semiconductor transistor. A display device may include the scan driver” see “Referring to FIG. 4, the inverter 220 according to the exemplary embodiment of the present disclosure may include a first transistor M1 and a second transistor M2 which are complementarily operated” “the first transistor M1 may be formed of a P-type polysilicon transistor” “the second transistor M2 may be formed of an N-type oxide semiconductor transistor” “In order to secure a rapid driving speed, the first transistor T1 may be formed of a polysilicon transistor. Further, the first transistor T1 may be formed of a p-type transistor” “the inverter 220 of the present invention includes the oxide semiconductor transistor M2 having a small leakage current, thereby decreasing power consumption”.
The Examiner notes that polysilicon is polycrystalline silicon.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Lee to include wherein the scan driver comprises: a first transistor disposed on the substrate and comprising a first semiconductor layer comprising an oxide semiconductor and a first gate electrode overlapping the first semiconductor layer; a second transistor disposed on the substrate and comprising a second semiconductor layer comprising a silicon semiconductor and a second gate electrode overlapping the second semiconductor layer; and insulating layers disposed on the substrate and defining dummy holes not overlapping the first semiconductor layer and the second semiconductor layer, wherein the dummy holes are spaced apart from the first semiconductor layer and the second semiconductor layer and overlap dummy semiconductor layers adjacent to the first semiconductor layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to get a scan driver with the desired high speed and low leakage and to use dummy circuitry and contact holes to control density of the photoresist pattern in the non-display area NDA.
In regard to claim 2 Lee and Shin as combined does not specifically teach wherein, in a plan view, a shortest distance between the dummy holes and the first semiconductor layer is 10 μm or less.
However see the purpose of the dummy patterns is to control density of the photoresist pattern across the chip and see that density in a display determines desirable properties such as resolution.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein, in a plan view, a shortest distance between the dummy holes and the first semiconductor layer is 10 μm or less ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 4 Lee and Shin as combined teaches wherein the dummy semiconductor layers are disposed on a same layer [see combination, the dummy circuitry is identical to the real circuitry except it is a dummy only for obtaining the density] as the second semiconductor layer and comprise a same material as a material of the second semiconductor layer.
In regard to claim 20 Lee and Shin as combined teaches wherein the scan driver comprises a plurality of stages [see combination, see Shin “A scan driver, includes a plurality of stage circuits, each of which includes a driving circuit unit providing an output signal and an inverter inverting the output signal of the driving circuit unit and generating a scan signal, in which the inverter includes a first transistor and a second transistor, which are complementarily operated, the first transistor is a P-type polysilicon transistor, and the second transistor is an N-type oxide semiconductor transistor”] and has an output terminal electrically corresponding to a scan line corresponding to each of the plurality of stages, and the first transistor of the scan driver is electrically connected to the output terminal.
Claim(s) 3, 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee and Shin as combined and further in view of Choi et al. (US 20100176395 A1) hereafter referred to as Choi
In regard to claim 3 Lee and Shin as combined does not specifically teach wherein, in a plan view, the first semiconductor layer comprises through holes, and the dummy semiconductor layers are respectively in the through holes of the first semiconductor layer.
See Choi teaches, see Fig. 2 see “a CMOS (complimentary metal oxide semiconductor) thin film transistor arrangement implemented by laminating a PMOS poly-silicon thin film transistor and an NMOS oxide thin film transistor” for use in display, see the gaps in “an oxide semiconductor layer 35, used as an active layer of a second thin film transistor” are used to contact the source and drain of “poly-silicon layer 10 is produced by depositing and crystallizing an amorphous silicon layer. In the poly-silicon layer 10, a source region 10a and a drain region 10b are produced by an ion injection technique”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Lee to include wherein, in a plan view, the first semiconductor layer comprises through holes, and the dummy semiconductor layers are respectively in the through holes of the first semiconductor layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to save space by stacking transistors.
In regard to claim 5 Lee, Shin and Choi as combined teaches wherein the insulating layers comprise a first insulating layer [see combination stacking transistors, see Choi Fig. 2, see 20, 25, 50 are insulators] covering the second semiconductor layer and a second insulating layer disposed on the first insulating layer and covering the first semiconductor layer, and the dummy holes penetrate [see combination, see Choi Fig. 2] the first insulating layer and the second insulating layer.
Conclusion
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893