DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species A, Claims 1-3, 5-12, and 14-18 in the reply filed on 04/06/2026 is acknowledged. The traversal is on the ground that Species A and Species B are not mutually exclusive. Species B appears to recite a narrower implementation of the doped portion . This is not found persuasive because as described in the restriction Species A refers to Fig. 2 while Species B refers to Fig. 3. The layers in these two figures are mutually exclusive hence the need for restriction..
The requirement is still deemed proper and is therefore made FINAL.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN202310520608.6, filed on 05/09/2023.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-7, 10 and 15-16 are rejected under U.S.C. 103 as being unpatentable over Liu et al.; US 2021/0215984 A1; 11/2019 in view of Zhang et al.; US 11,574,934 B2; 12/2017
Claim 1: Liu discloses an array substrate, comprising: a substrate ( Fig. 7 base 1 ); a first metal layer ( Fig. 7 metal layer 2 ), disposed on one side of the substrate ( Fig. 7 #1 ), wherein the first metal layer comprises a first connecting line ( [0029] The signal line 2 includes a light absorbing layer 21 and a metal layer 22 that are stacked in a direction away from the base 1 ); a gate insulating layer ( Fig. 7 gate insulating layer 11 ), disposed on a side of the first metal layer ( as shown in Fig. 7 ) facing away from the substrate ( Fig. 7 #1 ), wherein the gate insulating layer ( Fig. 7 #11 ) comprises a via hole ( Fig. 7 conductive connecting line 5 ) ; a second metal layer ( Fig. 7 #3 ), disposed on a side of the gate insulating layer ( Fig. 7 #11 ) facing away ( as shown in Fig. 7 ) from the first metal layer ( Fig. 7 #2 ), wherein the second metal layer ( Fig. 7 #6 ) comprises a second connecting line ( [0035] The array substrate further includes a signal line 2 arranged correspondingly to each of the at least one common electrode 3 ); and a pixel electrode layer ( Fig. 7 pixel electrode 6 ), disposed on a side of the second metal layer ( Fig. 7 #3 ) facing away from the gate insulating layer ( Fig. 7 #11 ), wherein the pixel electrode layer ( Fig. 7 #6 ) comprises a third connecting line ( [0034] a pixel electrode 6 located at a side of each common electrode 3 away from the base 1 );
Liu does not appear to disclose the array substrate further comprises a cushioning structure, the cushioning structure is disposed between the second connecting line and the gate insulating layer, a side of the cushioning structure close to the via hole extends beyond the second connecting line, the third connecting line overlaps with the second connecting line and a portion of the cushioning structure that extends beyond the second connecting line, the third connecting line is connected to the first connecting line through the via hole, and the cushioning structure is in insulated contact with the second connecting line.
However, Zhang teaches the array substrate further comprises a cushioning structure ( Fig. 1 first insulating layer 107 ), the cushioning structure ( Fig. 1 #107 ) is disposed between the second connecting line ( Fig. 1 source-drain metal layer 108 ) and the gate insulating layer ( Fig. 1 gate insulating layer 105 ), a side of the cushioning structure ( Fig. 1 #107 ) close to the via hole ( Fig. 2 via hole 1; Col. 8 lines 32 – 39 blocking the via hole 1 running through the first insulating layer 107 ) extends beyond the second connecting line ( Fig. 1 #108 ), the third connecting line ( Fig. 1 source electrode 1081 ) overlaps with the second connecting line ( Fig. 1 #108 ) and a portion of the cushioning structure ( Fig. 1 #107 ) that extends beyond the second connecting line ( Fig. 1 #108 ), the third connecting line ( Fig. 1 #1081 ) is connected to the first connecting line ( Fig. 1 drain electrode 1082; Col. 8 lines 18 – 20 the source-drain metal layer 108 includes a source electrode 1081 and a drain electrode 1082 ) through the via hole ( Fig. 1 #1 ), and the cushioning structure ( Fig. 1 #107 ) is in insulated contact with the second connecting line ( Fig. 1 #108 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Zhang with Liu to implement the array substrate further comprises a cushioning structure, the cushioning structure is disposed between the second connecting line and the gate insulating layer, a side of the cushioning structure close to the via hole extends beyond the second connecting line, the third connecting line overlaps with the second connecting line and a portion of the cushioning structure that extends beyond the second connecting line, the third connecting line is connected to the first connecting line through the via hole, and the cushioning structure is in insulated contact with the second connecting line because the cushioning structure is used to absorb mechanical stress and protect the substrate and pixel layers while maintaining electrical isolation and precise alignment of multi-layer electrodes.
Claim 6: Liu and Zhang disclose the array substrate according to claim 1 ( as discussed above ).
Liu does not appear to disclose a cushioning layer and an active layer, wherein the cushioning layer is disposed between the gate insulating layer and the second metal layer, and the cushioning layer comprises the cushioning structure.
However, Zhang teaches a cushioning layer ( Fig. 1 #107 ) and an active layer ( Fig. 1 active layer 104 ), wherein the cushioning layer ( Fig. 1 #107 ) is disposed between the gate insulating layer ( Fig. 1 #105 ) and the second metal layer ( Fig. 1 pixel electrode layer 112 ), and the cushioning layer ( Fig. 1 #107 ) comprises the cushioning structure ( Col 7 lines 20 – 43 forming a first insulating layer covering the gate metal layer, and forming a via hole running through the first insulating layer ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Zhang with Liu to implement a cushioning layer and an active layer, wherein the cushioning layer is disposed between the gate insulating layer and the second metal layer, and the cushioning layer comprises the cushioning structure because an active layer is included for device functionality and a cushioning layer to protect, stabilize and enhance the active layers performance.
Claim 7: Liu and Zhang disclose the array substrate according to claim 1 ( as discussed above ).
Liu does not appear to disclose an orthographic projection of the cushioning structure projected on the substrate is in contact with an orthographic projection of the via hole projected on the substrate.
However, Zhang teaches an orthographic projection ( as shown in Fig. 1 ) of the cushioning structure ( Fig. 1 #107 ) projected on the substrate ( Fig. 1 #101 ) is in contact with an orthographic projection ( as shown in Fig. 1 ) of the via hole ( Fig. 2 via hole 1 in area 1081 shown in Fig. 1 ) in projected on the substrate ( Fig. 1 #101 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Zhang with Liu to implement an orthographic projection of the cushioning structure projected on the substrate is in contact with an orthographic projection of the via hole projected on the substrate because an orthographic projection is used to ensure proper spatial alignment of 3D microstructures relative to substrate features.
Claim 10: Liu discloses a display panel (Fig. 9 display device 1000 ), comprising an array substrate ( Fig. 9 array substrate 1001 ), the array substrate ( Fig. 9 #1001 ) comprising: a substrate ( Fig. 9 base 1 ); a first metal layer ( Fig. 9 #2 ), disposed on one side of the substrate ( Fig. 9 #1 ), wherein the first metal layer comprises a first connecting line ( Fig. 9 #22 )); a gate insulating layer ( Fig. 9 #11 ), disposed on a side of the first metal layer ( Fig. 9 #2 ) facing away from the substrate ( Fig. 9 #1 ), wherein the gate insulating layer ( Fig. 9 #11 ) comprises a via hole ( Fig. 9 #5 ): a second metal layer ( Fig. 9 #3 ), disposed on a side of the gate insulating layer ( Fig. 9 #11 ) facing away from the first metal layer ( Fig. 9 #22 ), wherein the second metal layer ( Fig. 9 #3 ) comprises a second connecting line ( [0035] The array substrate further includes a signal line 2 arranged correspondingly to each of the at least one common electrode 3 ): and a pixel electrode layer ( Fig. 9 #6 ), disposed on a side of the second metal layer ( Fig. 9 #3 ) facing away from the gate insulating layer ( Fig. 9 #11 ), wherein the pixel electrode layer ( Fig. 9 #6 ) comprises a third connecting line ( [0034] a pixel electrode 6 located at a side of each common electrode 3 away from the base 1 );
Lui does not appear to disclose the array substrate further comprises a cushioning structure, the cushioning structure is disposed between the second connecting line and the gate insulating layer, a side of the cushioning structure close to the via hole extends beyond the second connecting line, the third connecting line overlaps with the second connecting line and a portion of the cushioning structure that extends beyond the second connecting line, the third connecting line is connected to the first connecting line through the via hole, and the cushioning structure is in insulated contact with the second connecting line.
However, Zhang teaches the array substrate further comprises a cushioning structure ( Fig. 1 first insulating layer 107 ), the cushioning structure ( Fig. 1 #107 ) is disposed between the second connecting line ( Fig. 1 source-drain metal layer 108 ) and the gate insulating layer ( Fig. 1 gate insulating layer 105 ), a side of the cushioning structure ( Fig. 1 #107 ) close to the via hole ( Fig. 2 via hole 1; Col. 8 lines 32 – 39 blocking the via hole 1 running through the first insulating layer 107 ) extends beyond the second connecting line ( Fig. 1 #108 ), the third connecting line ( Fig. 1 source electrode 1081 ) overlaps with the second connecting line ( Fig. 1 #108 ) and a portion of the cushioning structure ( Fig. 1 #107 ) that extends beyond the second connecting line ( Fig. 1 #108 ), the third connecting line ( Fig. 1 #1081 ) is connected to the first connecting line ( Fig. 1 drain electrode 1082; Col. 8 lines 18 – 20 the source-drain metal layer 108 includes a source electrode 1081 and a drain electrode 1082 ) through the via hole ( Fig. 1 #1 ), and the cushioning structure ( Fig. 1 #107 ) is in insulated contact with the second connecting line ( Fig. 1 #108 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Zhang with Liu to implement the array substrate further comprises a cushioning structure, the cushioning structure is disposed between the second connecting line and the gate insulating layer, a side of the cushioning structure close to the via hole extends beyond the second connecting line, the third connecting line overlaps with the second connecting line and a portion of the cushioning structure that extends beyond the second connecting line, the third connecting line is connected to the first connecting line through the via hole, and the cushioning structure is in insulated contact with the second connecting line because integrating a cushioning structure and a semiconductor layer satisfy mechanical robustness and electrical performance.
Claim 15: Liu and Zhang disclose the array substrate according to claim 10 ( as discussed above ).
Liu does not appear to disclose a cushioning layer and an active layer, wherein the cushioning layer is disposed between the gate insulating layer and the second metal layer, and the cushioning layer comprises the cushioning structure.
However, Zhang teaches a cushioning layer ( Fig. 1 #107 ) and an active layer ( Fig. 1 active layer 104 ), wherein the cushioning layer ( Fig. 1 #107 ) is disposed between the gate insulating layer ( Fig. 1 #105 ) and the second metal layer ( Fig. 1 pixel electrode layer 112 ), and the cushioning layer ( Fig. 1 #107 ) comprises the cushioning structure ( Col 7 lines 20 – 43 forming a first insulating layer covering the gate metal layer, and forming a via hole running through the first insulating layer ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Zhang with Liu to implement a cushioning layer and an active layer, wherein the cushioning layer is disposed between the gate insulating layer and the second metal layer, and the cushioning layer comprises the cushioning structure because the cushioning layer provides mechanical support, stress buffering, and defect reduction while the active layer is where the primary functionality occurs.
Claim 16: Liu and Zhang disclose the array substrate according to claim 10 ( as discussed above ).
Liu does not appear to disclose an orthographic projection of the cushioning structure projected on the substrate is in contact with an orthographic projection of the via hole projected on the substrate.
However, Zhang teaches an orthographic projection ( as shown in Fig. 1 ) of the cushioning structure ( Fig. 1 #107 ) projected on the substrate ( Fig. 1 #101 ) is in contact with an orthographic projection ( as shown in Fig. 1 ) of the via hole ( Fig. 2 via hole 1 in area 1081 shown in Fig. 1 ) in projected on the substrate ( Fig. 1 #101 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Zhang with Liu to implement an orthographic projection of the cushioning structure projected on the substrate is in contact with an orthographic projection of the via hole projected on the substrate because this provides a precise 2D visualization of 3D layer interactions.
Claims 2, 3, and 11-12 are rejected under U.S.C. 103 as being unpatentable over Liu et al.; US 2021/0215984 A1; 11/2019 in view of Zhang et al.; US 11,574,934 B2; 12/2017 as it relates to claim 1 above and further in view of Song et al.; US 2024/0142837 A1; 04/2022
Claim 2: Liu and Zhang disclose the array substrate according to claim 1 ( as discussed above).
Liu discloses an active layer ( Fig. 7 active layer 8 ), wherein the active layer ( Fig. 7 #8 ) is disposed between the gate insulating layer ( Fig. 7 gate insulating layer 11 ) and the second metal layer ( Fig. 7 drain 7 )
Neither Liu nor Zhang appear to disclose the active layer comprises an active pattern and the cushioning structure, and the cushioning structure is electrically insulated from the active pattern.
However, Song teaches the active layer ( Fig. 1: active layer 40 ) comprises an active pattern ( Fig. 1: first active pattern 401 ) and the cushioning structure ( Fig. 1: second active pattern 402 ), and the cushioning structure is electrically insulated from the active pattern ( [0060] The second active pattern 402 includes a second intrinsic part 4021, a second heavily-doped part 4022, and a second lightly-doped part 4023 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Song with Liu and Zhang to implement the active layer comprises an active pattern and the cushioning structure, and the cushioning structure is electrically insulated from the active pattern because an active pattern performs an electrical function and the cushioning structure provides mechanical stability, electrical isolation, and process reliability.
Claim 3: Liu, Zhang, and Song disclose the array substrate according to claim 2 ( as discussed above ).
Neither Liu nor Zhang appear to disclose the active pattern comprises a doped portion and a channel portion, and a dopant ion concentration of the cushioning structure is greater than or equal to a dopant ion concentration of the channel portion.
However, Song teaches the active pattern ( Fig. 1 active pattern 402 ) comprises a doped portion ( Fig. 1 second heavily-doped part 4022 ) and a channel portion ( Fig. 1 second intrinsic part 4021 ), and a dopant ion concentration of the cushioning structure ( Fig. 1 #402 ) is greater than or equal to a dopant ion concentration of the channel portion ( [0060] The second intrinsic part 4021 is a semiconductor ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Song with Liu and Zhang to implement the active pattern comprises a doped portion and a channel portion, and a dopant ion concentration of the cushioning structure is greater than or equal to a dopant ion concentration of the channel portion because the channel portion is where current regulation occurs.
Claim 11: Liu and Zhang disclose the array substrate according to claim 10 ( as discussed above).
Liu discloses an active layer ( Fig. 7 active layer 8 ), wherein the active layer ( Fig. 7 #8 ) is disposed between the gate insulating layer ( Fig. 7 gate insulating layer 11 ) and the second metal layer ( Fig. 7 drain 7 )
Neither Liu nor Zhang appear to disclose the active layer comprises an active pattern and the cushioning structure, and the cushioning structure is electrically insulated from the active pattern.
However, Song teaches the active layer ( Fig. 1: active layer 40 ) comprises an active pattern ( Fig. 1: first active pattern 401 ) and the cushioning structure ( Fig. 1: second active pattern 402 ), and the cushioning structure is electrically insulated from the active pattern ( [0060] The second active pattern 402 includes a second intrinsic part 4021, a second heavily-doped part 4022, and a second lightly-doped part 4023 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Song with Liu and Zhang to implement the active layer comprises an active pattern and the cushioning structure, and the cushioning structure is electrically insulated from the active pattern because the active pattern provides the functional electronic path for current and switching while the cushioning structure offers mechanical, electrical, and optical protection.
Claim 12: Liu, Zhang, and Song disclose the array substrate according to claim 11 ( as discussed above ).
Neither Liu nor Zhang appear to disclose the active pattern comprises a doped portion and a channel portion, and a dopant ion concentration of the cushioning structure is greater than or equal to a dopant ion concentration of the channel portion.
However, Song teaches the active pattern ( Fig. 1 active pattern 402 ) comprises a doped portion ( Fig. 1 second heavily-doped part 4022 ) and a channel portion ( Fig. 1 second intrinsic part 4021 ), and a dopant ion concentration of the cushioning structure ( Fig. 1 #402 ) is greater than or equal to a dopant ion concentration of the channel portion ( [0060] The second intrinsic part 4021 is a semiconductor ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Song with Liu and Zhang to implement the active pattern comprises a doped portion and a channel portion, and a dopant ion concentration of the cushioning structure is greater than or equal to a dopant ion concentration of the channel portion because this approach fulfills complementary roles for high-performance transistor operation and reliable interconnection.
Claims 5 and 14 are rejected under U.S.C. 103 as being unpatentable over Liu et al.; US 2021/0215984 A1; 11/2019 in view of Zhang et al.; US 11,574,934 B2; 12/2017 and Song et al.; US 2024/0142837 A1; 04/2022 as it relates to claim 3 above and further in view of Li et al.; US 2024/0222379 A1; 11/2022 and Kim et al.; US 2011/0175869 A1; 05/2010
Claim 5: Liu, Zhang, and Song disclose the array substrate according to claim 3 ( as discussed above ).
Neither Liu nor Zhang appear to disclose the doped portion comprises a plurality of parts, and the second metal layer further comprises a source electrode and a drain electrode; and wherein the source electrode and the drain electrode are respectively connected to the plurality of parts of the doped portion, the doped portion is in contact with the channel portion, and the dopant ion concentration of the cushioning structure is equal to the dopant ion concentration of the channel portion.
Song discloses the doped portion comprises a plurality of parts ( Fig. 1 second heavily-doped part 4022 and second lightly-doped part 4023 ).
Song does not appear to disclose the second metal layer further comprises a source electrode and a drain electrode; and wherein the source electrode and the drain electrode are respectively connected to the plurality of parts of the doped portion, the doped portion is in contact with the channel portion, and the dopant ion concentration of the cushioning structure is equal to the dopant ion concentration of the channel portion.
Li discloses the second metal layer ( [0066] In the embodiment of the present disclosure, a source/drain metal layer corresponds to the source electrode 201 and the drain electrode 202, respectively ) further comprises a source electrode ( Fig. 1 #201 ) and a drain electrode ( Fig. 1 #202 ); and wherein the source electrode ( Fig. 1 #201 ) and the drain electrode ( Fig. 1 #202 ) are respectively connected to the plurality of parts of the doped portion ( [0033] the source/drain metal layer is disposed on surfaces of the heavily doped areas of the second active layer ), the doped portion ( Fig. 1 second active layer 32 ) is in contact with the channel portion ( Fig. 1 second channel area 323 ).
Li does not appear to disclose the dopant ion concentration of the cushioning structure is equal to the dopant ion concentration of the channel portion.
However, Kim teaches the dopant ion concentration ( [0089] The active layer 131 having amorphous silicon (a-Si) and the resistant contact layer 132 having amorphous silicon doped with N type dopants at a high concentration (n+a-Si), are sequentially deposited on the gate insulating layer 120 and patterned to form the channel portion CH in the display area DA and to form the channel layer 130 in the circuit area CA ) of the cushioning structure ( Fig. 5A resistant contact layer 132 ) is equal to the dopant ion concentration ( as discussed above ) of the channel portion ( Fig. 5A channel layer 130 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kim with Liu, Zhang, Song, and Li to implement the second metal layer further comprises a source electrode and a drain electrode; and wherein the source electrode and the drain electrode are respectively connected to the plurality of parts of the doped portion, the doped portion is in contact with the channel portion, and the dopant ion concentration of the cushioning structure is equal to the dopant ion concentration of the channel portion because this approach provides structural context and is a necessity for source and drain electrodes in the second metal layer.
Claim 14: Liu, Zhang, and Song disclose the array substrate according to claim 12 ( as discussed above ).
Neither Liu nor Zhang appear to disclose the doped portion comprises a plurality of parts, and the second metal layer further comprises a source electrode and a drain electrode; and wherein the source electrode and the drain electrode are respectively connected to the plurality of parts of the doped portion, the doped portion is in contact with the channel portion, and the dopant ion concentration of the cushioning structure is equal to the dopant ion concentration of the channel portion.
Song discloses the doped portion comprises a plurality of parts ( Fig. 1 second heavily-doped part 4022 and second lightly-doped part 4023 ).
Song does not appear to disclose the second metal layer further comprises a source electrode and a drain electrode; and wherein the source electrode and the drain electrode are respectively connected to the plurality of parts of the doped portion, the doped portion is in contact with the channel portion, and the dopant ion concentration of the cushioning structure is equal to the dopant ion concentration of the channel portion.
Li discloses the second metal layer ( [0066] In the embodiment of the present disclosure, a source/drain metal layer corresponds to the source electrode 201 and the drain electrode 202, respectively ) further comprises a source electrode ( Fig. 1 #201 ) and a drain electrode ( Fig. 1 #202 ); and wherein the source electrode ( Fig. 1 #201 ) and the drain electrode ( Fig. 1 #202 ) are respectively connected to the plurality of parts of the doped portion ( [0033] the source/drain metal layer is disposed on surfaces of the heavily doped areas of the second active layer ), the doped portion ( Fig. 1 second active layer 32 ) is in contact with the channel portion ( Fig. 1 second channel area 323 ).
Li does not appear to disclose the dopant ion concentration of the cushioning structure is equal to the dopant ion concentration of the channel portion.
However, Kim teaches the dopant ion concentration ( [0089] The active layer 131 having amorphous silicon (a-Si) and the resistant contact layer 132 having amorphous silicon doped with N type dopants at a high concentration (n+a-Si), are sequentially deposited on the gate insulating layer 120 and patterned to form the channel portion CH in the display area DA and to form the channel layer 130 in the circuit area CA ) of the cushioning structure ( Fig. 5A resistant contact layer 132 ) is equal to the dopant ion concentration ( as discussed above ) of the channel portion ( Fig. 5A channel layer 130 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kim with Liu, Zhang, Song, and Li to implement the second metal layer further comprises a source electrode and a drain electrode; and wherein the source electrode and the drain electrode are respectively connected to the plurality of parts of the doped portion, the doped portion is in contact with the channel portion, and the dopant ion concentration of the cushioning structure is equal to the dopant ion concentration of the channel portion because this approach provides structural context and is a necessity for source and drain electrodes in the second metal layer.
Claim 8 and 17 are rejected under U.S.C. 103 as being unpatentable over Liu et al.; US 2021/0215984 A1; 11/2019 in view of Zhang et al.; US 11,574,934 B2; 12/2017 as it relates to claim 1 above and further in view of An et al.; US 2026/0020346 A1; 12/2022
Claim 8: Liu and Zhang disclose the array substrate according to claim 1 ( as discussed above).
Neither Liu nor Zhang appear to disclose a spacing between a side surface of the side of the cushioning structure close to the via hole and a side surface of a side of the second connecting line close to the via hole is greater than or equal to 1 micrometer.
However, An teaches a spacing between a side surface of the side of the cushioning structure ( Fig. 12 recessed portion 33 ) close to the via hole ( Fig. 12 third via hole 42 ) and a side surface of a side of the second connecting line ( Fig. 12 second conductive strip 52 ) close to the via hole ( Fig. 12 #42 ) is greater than or equal to 1 micrometer ( [0150] The spacing between the edge line of the orthographic projection of the third via hole 42 on the first base substrate 1 and the adjacent second conductive strip 52 is greater than or equal to 0.5 micrometers and less than or equal to 3 micrometers. ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of An with Liu and Zhang to implement a spacing between a side surface of the side of the cushioning structure close to the via hole and a side surface of a side of the second connecting line close to the via hole is greater than or equal to 1 micrometer because this approach provides electrical isolation and mechanical buffering.
Claim 17: Liu and Zhang disclose the array substrate according to claim 10 ( as discussed above).
Neither Liu nor Zhang appear to disclose a spacing between a side surface of the side of the cushioning structure close to the via hole and a side surface of a side of the second connecting line close to the via hole is greater than or equal to 1 micrometer.
However, An teaches a spacing between a side surface of the side of the cushioning structure ( Fig. 12 recessed portion 33 ) close to the via hole ( Fig. 12 third via hole 42 ) and a side surface of a side of the second connecting line ( Fig. 12 second conductive strip 52 ) close to the via hole ( Fig. 12 #42 ) is greater than or equal to 1 micrometer ( [0150] The spacing between the edge line of the orthographic projection of the third via hole 42 on the first base substrate 1 and the adjacent second conductive strip 52 is greater than or equal to 0.5 micrometers and less than or equal to 3 micrometers ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of An with Liu and Zhang to implement a spacing between a side surface of the side of the cushioning structure close to the via hole and a side surface of a side of the second connecting line close to the via hole is greater than or equal to 1 micrometer because this approach provides electrical isolation and mechanical buffering.
Claim 9 and 18 are rejected under U.S.C. 103 as being unpatentable over Liu et al.; US 2021/0215984 A1; 11/2019 in view of Zhang et al.; US 11,574,934 B2; 12/2017 as it relates to claim 1 above and further in view of Wang; US 2024/0204003 A1; 01/2021
Claim 9: Liu and Zhang disclose the array substrate according to claim 1 ( as discussed above ).
Neither Liu nor Zhang appear to disclose a material of the cushioning structure comprises one selected from a group consisting of indium gallium zinc oxide, zinc oxide, tin oxide, indium zinc oxide, gallium zinc oxide, zinc tin oxide, and indium tin oxide.
However, Wang teaches a material of the cushioning structure ( Fig. 1 first transparent insulating layer 140 ) comprises one selected from a group consisting of indium gallium zinc oxide, zinc oxide, tin oxide, indium zinc oxide, gallium zinc oxide, zinc tin oxide, and indium tin oxide ( [0021] the material of the first transparent insulating layer is any one of silicon oxide, silicon oxynitride, indium tin oxide, aluminum oxide, conductorized indium gallium zinc oxide, conductorized indium zinc oxide, or conductorized indium gallium zinc tin oxide ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang with Liu and Zhang to implement a material of the cushioning structure comprises one selected from a group consisting of indium gallium zinc oxide, zinc oxide, tin oxide, indium zinc oxide, gallium zinc oxide, zinc tin oxide, and indium tin oxide because these materials provide optical transparency which is essential for display substrates.
Claim 18: Liu and Zhang disclose the array substrate according to claim 10 ( as discussed above ).
Neither Liu nor Zhang appear to disclose a material of the cushioning structure comprises one selected from a group consisting of indium gallium zinc oxide, zinc oxide, tin oxide, indium zinc oxide, gallium zinc oxide, zinc tin oxide, and indium tin oxide.
However, Wang teaches a material of the cushioning structure ( Fig. 1 first transparent insulating layer 140 ) comprises one selected from a group consisting of indium gallium zinc oxide, zinc oxide, tin oxide, indium zinc oxide, gallium zinc oxide, zinc tin oxide, and indium tin oxide ( [0021] the material of the first transparent insulating layer is any one of silicon oxide, silicon oxynitride, indium tin oxide, aluminum oxide, conductorized indium gallium zinc oxide, conductorized indium zinc oxide, or conductorized indium gallium zinc tin oxide ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang with Liu and Zhang to implement a material of the cushioning structure comprises one selected from a group consisting of indium gallium zinc oxide, zinc oxide, tin oxide, indium zinc oxide, gallium zinc oxide, zinc tin oxide, and indium tin oxide because these materials provide optical transparency which is essential for display substrates.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights