Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: P202300510US01
Filling Date: 11/15/2023
Applicant: Anderson et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-7 and 15-20 in the reply filed on 01/13/2026 is acknowledged.
Claims 8-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 15, 17-18 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Alaan et al (US 2023/0187509 A1).
Regarding claim 1, Alaan discloses a semiconductor structure (Fig. 2L) comprising: a first transistor 238 (Para. 51) on a substrate 102 (Para. 20); a second transistor 240 (Para. 51) on top of the first transistor 238; and a source/drain (S/D) contact 236 (Para. 49) contacting a first S/D region 220, 234 (Paras. 41, 48) of the first transistor 238, wherein the S/D contact 236 has a horizontal portion (portion underneath 228) and a vertical portion 236 (middle portion), the horizontal portion (portion underneath 228) extending from a sidewall of the vertical portion 236 (portion between 228 and 230) and a portion of the horizontal portion 236 (portion underneath 228) being vertically between the first S/D region 220, 234 of the first transistor 238 and a second S/D region 228 (Para. 49) of the second transistor 240.
Regarding claim 2, Alaan discloses the semiconductor structure of claim 1, wherein a portion of the first S/D region 220, 234 of the first transistor 238 is vertically outside the second S/D region 228 of the second transistor 240.
Regarding claim 3, Alaan discloses the semiconductor structure of claim 2, wherein a bottom surface of the vertical portion of the S/D contact 236 is in direct contact with the portion of the first S/D region 220, 234 of the first transistor 238 and is below the horizontal portion of the S/D contact 236 (portion underneath 228).
Regarding claim 4, Alaan discloses the semiconductor structure of claim 2, wherein a portion of the sidewall of the vertical portion of the S/D contact 236 is in direct contact with the portion of the first S/D region 220, 234 of the first transistor 238 and is below the horizontal portion of the S/D contact 236.
Regarding claim 5, Alaan discloses the semiconductor structure of claim 1, wherein the horizontal portion of the S/D contact 236 is horizontally in contact with a dummy sheet 234, the dummy sheet 234 being directly on top of the first S/D region 220 of the first transistor 238.
Regarding claim 15, Alaan discloses a semiconductor structure (Fig. 2L) comprising: a first nanosheet transistor 238 (Para. 51) on a substrate 102 (Para. 20); a second nanosheet transistor 240 (Para. 51) on top of the first nanosheet transistor 238; and a source/drain (S/D) contact 236 (Para. 49) contacting a first S/D region 220, 234 (Paras. 41, 48) of the first nanosheet transistor 238, wherein the S/D contact 236 has a horizontal portion 236 (portion underneath 228) and a vertical portion 236 (portion between 228 and 230), the horizontal portion 236 extending from a sidewall of the vertical portion 236 and covering a top surface of the first S/D region 234, 220 of the first nanosheet transistor 238.
Regarding claim 17, Alaan discloses the semiconductor structure of claim 16, wherein a bottom surface of the vertical portion of the S/D contact 236 is in direct contact with the portion of the first S/D region 234, 220 of the first nanosheet transistor 238 and is below the horizontal portion of the S/D contact 236.
Regarding claim 18, Alaan discloses the semiconductor structure of claim 16, wherein a portion of the sidewall of the vertical portion of the S/D contact 236 is in direct contact with the portion of the first S/D region 236 of the first nanosheet transistor 238 and is below the horizontal portion of the S/D contact 236.
Regarding claim 19, Alaan discloses the semiconductor structure of claim 15, wherein at least a portion of the horizontal portion of the S/D contact 236 is vertically between the first S/D region 220, of the first nanosheet transistor 238 and the second S/D region of the second nanosheet transistor 240, and the horizontal portion of the S/D contact 236 is horizontally in contact with a dummy sheet 234, the dummy sheet 234 being directly on top of the first S/D region 220 of the first nanosheet transistor 238.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Alaan et al (US 2023/0187509 A1).
Regarding claim 6, Alaan discloses the semiconductor structure of claim 5, wherein the horizontal portion of the S/D contact 236 and the dummy sheet 234 are substantially coplanar (Fig. 2L).
Alaan does not explicitly disclose the horizontal portion of the S/D contact and the dummy sheet have a substantially same thickness.
However, Alaan teaches a particular thicknesses for the horizontal portion 236 (portion under 228) of the S/D contact and the dummy sheet 234 (Fig. 2L).
It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to obtain the horizontal portion of the S/D contact and the dummy sheet have a substantially same thickness for intended purposes.
the applicants have not established the criticality (see next paragraph below) of the thicknesses.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 20, Alaan discloses the semiconductor structure of claim 19, wherein the horizontal portion of the S/D contact 236 and the dummy sheet 238 have a substantially coplanar (Fig. 2L).
Alaan does not explicitly disclose the horizontal portion of the S/D contact and the dummy sheet have a substantially same thickness.
However, Alaan discloses a particular thicknesses for the horizontal portion of the S/D contact 236 (portion underneath 228) and the dummy sheet 234.
It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to obtain the horizontal portion of the S/D contact and the dummy sheet have a substantially same thickness for intended purposes.
the applicants have not established the criticality (see next paragraph below) of the thicknesses.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim(s) 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Alaan et al (US 2023/0187509 A1) in view of Yang et al (US 2021/0376137 A1).
Regarding claim 7, Alaan discloses the semiconductor structure of claim 1, wherein the first transistor 238 is a first nanosheet transistor having a first set of nanosheets 238 of a first width, the second transistor is a second nanosheet transistor 240 having a second set of nanosheets of a second width 240.
However, Yang discloses the second width 1840 (Figs. 17, 23, Para. 75) is narrower than the first width 122A (Figs. 17, 23, Para. 34). Yang teaches the above modification is used to reduce manufacturing complexity (Para. 1). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Alaan first width and second width with Yang first width and second width as suggested above to reduce manufacturing complexity (Para. 1).
Regarding claim 16, Alaan discloses the semiconductor structure of claim 15, wherein the first nanosheet transistor 238 has a first set of nanosheets 238 of a first width and the second nanosheet transistor 240 has a second set of nanosheets 240 of a second width; and wherein and a portion of the first S/D region 220, 134 of the first nanosheet transistor 238 is vertically outside the second S/D region 228 of the second nanosheet transistor 240.
Alaan does not explicitly disclose the second width being narrower than the first width.
However, Yang discloses the second width 1840 (Figs. 17, 23, Para. 75) being narrower than the first width 122A (Figs. 17, 23, Para. 34). Yang teaches the above modification is used to reduce manufacturing complexity (Para. 1). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Alaan first width and second width with Yang first width and second width as suggested above to reduce manufacturing complexity (Para. 1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817