DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 10, 16 have been amended.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-9, 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jones et al. (US9876709) in view of He et al. (US20250350301, App No. 19264333) further in view of Wang et al. (US20130262941).
Regarding claim 1, Jones teaches Alignment detection circuitry (Fig 2, Alignment detection circuitry 122 1-M) comprising: a buffer (Fig 2 “Buffer 202, 210) configured to output a data stream of multiplexed groups of symbols (col 4 lines 60 -67 “Each of the alignment detection circuits 122 receives an input data stream from a respective data lane. Each data stream includes multiplexed data, so the information transmitted on any single data lane cannot be correctly interpreted until aligned and recombined with information on the other data lanes. Each of the alignment detection circuits 122 outputs an aligned and de-skewed data stream on a respective data lane so that such recombination can be achieved”)
a first set of correlators (Fig. 2 Correlator 212, ) configured to search a candidate data lane of the data stream for bits matching bits of a reference alignment marker based on a first search method (col 6 lines 38-45 “The correlator 212 performs a correlation of each candidate block to detect an AM and determine the start location of the AM within the candidate block. In an example, the correlator 212 implements a synchronization state machine 214 that controls and tracks the AM synchronization process”, col 3 lines 33-36 “A correlator performs a more detailed analysis of only the candidate blocks to search for AMs, filters out any false positive matches, and establishes a start location in a data frame in case of a correct match”);
Jones does not explicitly teach a data stream of multiplexed groups of symbols from multiple data lanes, and a second set of correlators configured to search the candidate data lane of the data stream for bits matching the bits of the reference alignment marker based on a second search method, wherein the first set of correlators and the second set of correlators are configured to perform the search in parallel.
He teaches a data stream of multiplexed groups of symbols from multiple data lanes ([0007] “the first data stream is obtained by multiplexing the plurality of second data streams at the reference granularity of the quantity of bits corresponding to the n symbols included in the FEC codeword”),
and a second set of correlators configured to search the candidate data lane of the data stream for bits matching the bits of the reference alignment marker based on a second search method ([0019] “the search unit is further configured to: obtain a second data segment from a second location in the first data stream at the reference granularity based on no AM being found in the first data segment, where the second location is different from the first location; and perform AM search on the second data segment”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jones to incorporate the teachings of He. One of ordinary skill in the art would have been motivated to make this modification increase accuracy of receiving data.
He does not teach wherein the first set of correlators and the second set of correlators are configured to perform the search in parallel.
Wang teaches wherein the first set of correlators and the second set of correlators are configured to perform the search in parallel (Fig. 3 “304”, [0033] “The logic implementation 300, for example, includes a logic section 302 that compares a template pattern (tm[i]) for the MP for which the destination is searching against the input bits (in[i]). The XOR logic 304 finds mismatches between the template and the input bits, (XOR) (Examienr’s Note: XOR logic 304 could be broadly be interpreted as a correlator since the XOR are used to perform searching for mismatch” and there multiple xor logic 304 being performed in parallel”) .
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Jones, He to incorporate the teachings of Wang. One of ordinary skill in the art would have been motivated to make this modification into order to minimize error in data alignment..
Regarding claim 2, Jones does not explicitly teach wherein the first search method does not include an offset and the second search method includes the offset.
He teaches wherein the first search method does not include an offset and the second search method includes the offset ([0019] “the search unit is further configured to: obtain a second data segment from a second location in the first data stream at the reference granularity based on no AM being found in the first data segment, where the second location is different from the first location; and perform AM search on the second data segment”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jones to incorporate the teachings of He. One of ordinary skill in the art would have been motivated to make this modification increase accuracy of receiving data.
Regarding claim 3, Jones teaches wherein the offset is a number of bits included in a symbol (col 8 lines 10-17 “Before alignment, the AMs 302-1 through 302-5 are offset from the words 308-1 through 308-4 by X bits. An alignment detection circuit 122 operates as described above to process blocks of the frame 303, detect AMs, and adjust alignment of the frame 301 x with respect to the frame 303 so that the AMs 302-1 through 302-5 are aligned with the words 308-1 through 308-4.”).
Regarding claim 4, Jones teaches wherein the first set of correlators searches the candidate data lane of the data stream for bits matching a subset of the bits of the reference alignment marker (col 6 lines 38-45 “The correlator 212 performs a correlation of each candidate block to detect an AM and determine the start location of the AM within the candidate block. In an example, the correlator 212 implements a synchronization state machine 214 that controls and tracks the AM synchronization process”, col 3 lines 33-36 “A correlator performs a more detailed analysis of only the candidate blocks to search for AMs, filters out any false positive matches, and establishes a start location in a data frame in case of a correct match”).
Regarding claim 5, Jones teaches wherein the first set of correlators is configured to output at least one of a complete match of the subset or a partial match of the subset (col 6 lines 38-45 “The correlator 212 performs a correlation of each candidate block to detect an AM and determine the start location of the AM within the candidate block. In an example, the correlator 212 implements a synchronization state machine 214 that controls and tracks the AM synchronization process”, col 3 lines 33-36 “A correlator performs a more detailed analysis of only the candidate blocks to search for AMs, filters out any false positive matches, and establishes a start location in a data frame in case of a correct match”).
Regarding claim 6, Jones teaches further comprising first shifter circuitry of a first phase of shifting configured to add bit skew to the candidate data lane before the candidate data lane is locked (Fig. 2 “Alignment Control”, col 6 lines 45-50 “For example, the buffer 202 can adjust the alignment by adding or dropping one or more bits from the data stream”, (Examiner’s Note: Correlator performs alignment control before it outputs/locks data based on Fig 2, since the function being performed is adding or dropping bits, can be broadly defined as shifter).
Regarding claim 7, Jones teaches further comprising second shifter circuitry of a second phase of shifting configured to remove the bit skew from the candidate data lane after the candidate data lane is locked (col 4 lines 34-40 “Each of the alignment detection circuits 122 obtains a lock to AMs and locates frame boundaries in the data stream of a respective data lane. The alignment processor 117 removes skew from the data streams across the data lanes and provides M aligned and de-skewed data streams to the FEC processor 118”).
Regarding claim 8, Jone teaches wherein the second shifter circuitry of the second phase of shifting is further configured to remove lane skew from the data stream after the candidate data lane is locked (col 4 lines 34-40 “Each of the alignment detection circuits 122 obtains a lock to AMs and locates frame boundaries in the data stream of a respective data lane. The alignment processor 117 removes skew from the data streams across the data lanes and provides M aligned and de-skewed data streams to the FEC processor 118”).
Regarding claim 9, Jones teaches wherein the second shifter circuitry of the second phase of shifting is further configured to remove an offset from the candidate data lane after the candidate data lane is locked (col 4 lines 34-40 “Each of the alignment detection circuits 122 obtains a lock to AMs and locates frame boundaries in the data stream of a respective data lane. The alignment processor 117 removes skew from the data streams across the data lanes and provides M aligned and de-skewed data streams to the FEC processor 118”, (Examiner’s Note: skew is equivalent to offset).
Regarding claim 16, Jones teaches A method comprising: receiving a data stream of multiplexed groups of symbols (col 4 lines 60 -67 “Each of the alignment detection circuits 122 receives an input data stream from a respective data lane. Each data stream includes multiplexed data, so the information transmitted on any single data lane cannot be correctly interpreted until aligned and recombined with information on the other data lanes. Each of the alignment detection circuits 122 outputs an aligned and de-skewed data stream on a respective data lane so that such recombination can be achieved”)
searching, by a first correlator circuit using a first search algorithm, a candidate data lane of the data stream for bits matching bits of a reference alignment marker (col 6 lines 38-45 “The correlator 212 performs a correlation of each candidate block to detect an AM and determine the start location of the AM within the candidate block. In an example, the correlator 212 implements a synchronization state machine 214 that controls and tracks the AM synchronization process”, col 3 lines 33-36 “A correlator performs a more detailed analysis of only the candidate blocks to search for AMs, filters out any false positive matches, and establishes a start location in a data frame in case of a correct match”);
Jones does not teaches stream of multiplexed groups of symbols from multiple data lanes; and searching, by a second correlator circuit using a second search algorithm, the candidate data lane of the data stream for bits matching the bits of the reference alignment marker, wherein searching by the first correlator circuit and the second correlator circuit are performed in parallel.
He teaches stream of multiplexed groups of symbols from multiple data lanes ([0007] “the first data stream is obtained by multiplexing the plurality of second data streams at the reference granularity of the quantity of bits corresponding to the n symbols included in the FEC codeword”); and searching, by a second correlator circuit using a second search algorithm, the candidate data lane of the data stream for bits matching the bits of the reference alignment marker ([0019] “the search unit is further configured to: obtain a second data segment from a second location in the first data stream at the reference granularity based on no AM being found in the first data segment, where the second location is different from the first location; and perform AM search on the second data segment”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jones to incorporate the teachings of He. One of ordinary skill in the art would have been motivated to make this modification increase accuracy of receiving data.
He does not teach wherein searching by the first correlator circuit and the second correlator circuit are performed in parallel.
Wang teaches wherein searching by the first correlator circuit and the second correlator circuit are performed in parallel(Fig. 3 “304”, [0033] “The logic implementation 300, for example, includes a logic section 302 that compares a template pattern (tm[i]) for the MP for which the destination is searching against the input bits (in[i]). The XOR logic 304 finds mismatches between the template and the input bits, (XOR) (Examienr’s Note: XOR logic 304 could be broadly be interpreted as a correlator since the XOR are used to perform searching for mismatch” and there multiple xor logic 304 being performed in parallel”) .
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Jones, He to incorporate the teachings of Wang. One of ordinary skill in the art would have been motivated to make this modification into order to minimize error in data alignment.
Regarding claim 17, Jones does not teach wherein the first search algorithm does not utilize an offset and the second search algorithm utilizes the offset.
He teaches wherein the first search algorithm does not utilize an offset and the second search algorithm utilizes the offset ([0019] “the search unit is further configured to: obtain a second data segment from a second location in the first data stream at the reference granularity based on no AM being found in the first data segment, where the second location is different from the first location; and perform AM search on the second data segment”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jones to incorporate the teachings of He. One of ordinary skill in the art would have been motivated to make this modification increase accuracy of receiving data.
Regarding claim 18, Jones teaches further comprising adding bit skew to the candidate data lane in a first phase of shifting before the candidate data lane is locked (Fig. 2 “Alignment Control”, col 6 lines 45-50 “For example, the buffer 202 can adjust the alignment by adding or dropping one or more bits from the data stream”, (Examiner’s Note: Correlator performs alignment control before it outputs/locks data based on Fig 2, since the function being performed is adding or dropping bits, can be broadly defined as shifter).
Regarding claim 19, Jones teaches further comprising removing lane skew from the candidate data lane in a second phase of shifting after the candidate data lane is locked (col 4 lines 34-40 “Each of the alignment detection circuits 122 obtains a lock to AMs and locates frame boundaries in the data stream of a respective data lane. The alignment processor 117 removes skew from the data streams across the data lanes and provides M aligned and de-skewed data streams to the FEC processor 118”).
Regarding claim 20, Jones teaches further comprising removing the bit skew from the candidate data lane in a second phase of shifting after the candidate data lane is locked (col 4 lines 34-40 “Each of the alignment detection circuits 122 obtains a lock to AMs and locates frame boundaries in the data stream of a respective data lane. The alignment processor 117 removes skew from the data streams across the data lanes and provides M aligned and de-skewed data streams to the FEC processor 118”).
Claim(s) 10-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of He further in view of Jones (US10320516 herein Jones2) further in view of Wang.
Regarding claim 10, Jones teaches Receiver circuitry comprising: a first correlator circuit configured to search a candidate data lane of a data stream of multiplexed symbols for bits matching bits of a reference alignment marker based on a first search method (col 6 lines 38-45 “The correlator 212 performs a correlation of each candidate block to detect an AM and determine the start location of the AM within the candidate block. In an example, the correlator 212 implements a synchronization state machine 214 that controls and tracks the AM synchronization process”, col 3 lines 33-36 “A correlator performs a more detailed analysis of only the candidate blocks to search for AMs, filters out any false positive matches, and establishes a start location in a data frame in case of a correct match”);
and a selection circuit
Jones does not explicitly teach a second correlator circuit configured to search the candidate data lane of the data stream of the multiplexed symbols for bits matching the bits of the reference alignment marker based on a second search method; wherein the first correlator circuit and the second correlator circuit are configured to perform the search in parallel,
He teaches a second correlator circuit configured to search the candidate data lane of the data stream of the multiplexed symbols for bits matching the bits of the reference alignment marker based on a second search method ([0019] “the search unit is further configured to: obtain a second data segment from a second location in the first data stream at the reference granularity based on no AM being found in the first data segment, where the second location is different from the first location; and perform AM search on the second data segment”);
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jones to incorporate the teachings of He. One of ordinary skill in the art would have been motivated to make this modification increase accuracy of receiving data.
He does not teach wherein the first correlator circuit and the second correlator circuit are configured to perform the search in parallel,
Jones2 teaches and a selection circuit configured to select an output from at least one of the first correlator circuit or the second correlator circuit (col 14 lines 48-55 “A select circuit, which may be implemented as buffer-multiplexer circuit 336, may be configured to receive and buffer each of such streams of soft-decision values 324-1 through 324-N. Buffer-multiplexer circuit 336 may further be configured to receive each of marker detected signals 335 and to select each corresponding stream of soft-decision values responsive to assertion of corresponding ones of marker detected signal 335”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified He to incorporate the teachings of Jones2. One of ordinary skill in the art would have been motivated to make this modification in order to minimize to error due to noise .
Jones2 does not teach wherein the first correlator circuit and the second correlator circuit are configured to perform the search in parallel.
Wang teaches wherein the first correlator circuit and the second correlator circuit are configured to perform the search in parallel(Fig. 3 “304”, [0033] “The logic implementation 300, for example, includes a logic section 302 that compares a template pattern (tm[i]) for the MP for which the destination is searching against the input bits (in[i]). The XOR logic 304 finds mismatches between the template and the input bits, (XOR) (Examienr’s Note: XOR logic 304 could be broadly be interpreted as a correlator since the XOR are used to perform searching for mismatch” and there multiple xor logic 304 being performed in parallel”) .
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Jones, He, Jones2 to incorporate the teachings of Wang. One of ordinary skill in the art would have been motivated to make this modification into order to minimize error in data alignment.
Regarding claim 11, Jones teaches wherein the first correlator circuit searches the candidate data lane of the data stream for bits matching a subset of the bits of the reference alignment marker (col 6 lines 38-45 “The correlator 212 performs a correlation of each candidate block to detect an AM and determine the start location of the AM within the candidate block. In an example, the correlator 212 implements a synchronization state machine 214 that controls and tracks the AM synchronization process”, col 3 lines 33-36 “A correlator performs a more detailed analysis of only the candidate blocks to search for AMs, filters out any false positive matches, and establishes a start location in a data frame in case of a correct match”).
Regarding claim 12, Jones teaches further comprising a buffer (Fig 2 “Buffer 202, 210) configured to output the data stream of the multiplexed symbols to the first correlator circuit (col 4 lines 60 -67 “Each of the alignment detection circuits 122 receives an input data stream from a respective data lane. Each data stream includes multiplexed data, so the information transmitted on any single data lane cannot be correctly interpreted until aligned and recombined with information on the other data lanes. Each of the alignment detection circuits 122 outputs an aligned and de-skewed data stream on a respective data lane so that such recombination can be achieved”, Fig. 2 Correlator 212)
Jones does not teaches and the second correlator circuit.
He teaches and the second correlator circuit ([0019] “the search unit is further configured to: obtain a second data segment from a second location in the first data stream at the reference granularity based on no AM being found in the first data segment, where the second location is different from the first location; and perform AM search on the second data segment”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jones to incorporate the teachings of He. One of ordinary skill in the art would have been motivated to make this modification increase accuracy of receiving data.
Regarding claim 13, Jones teaches further comprising first shifter circuitry configured to add bit skew to the candidate data lane in a first phase of shifting before the candidate data lane is locked (Fig. 2 “Alignment Control”, col 6 lines 45-50 “For example, the buffer 202 can adjust the alignment by adding or dropping one or more bits from the data stream”, (Examiner’s Note: Correlator performs alignment control before it outputs/locks data based on Fig 2, since the function being performed is adding or dropping bits, can be broadly defined as shifter).
Regarding claim 14, Jones teaches further comprising second shifter circuitry configured to remove the bit skew from the candidate data lane in a second phase of shifting after the candidate data lane is locked (col 4 lines 34-40 “Each of the alignment detection circuits 122 obtains a lock to AMs and locates frame boundaries in the data stream of a respective data lane. The alignment processor 117 removes skew from the data streams across the data lanes and provides M aligned and de-skewed data streams to the FEC processor 118”).
Regarding claim 15, Jones does not teach wherein the first search method does not include an offset and the second search method includes the offset.
He teaches wherein the first search method does not include an offset and the second search method includes the offset ([0019] “the search unit is further configured to: obtain a second data segment from a second location in the first data stream at the reference granularity based on no AM being found in the first data segment, where the second location is different from the first location; and perform AM search on the second data segment”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jones to incorporate the teachings of He. One of ordinary skill in the art would have been motivated to make this modification increase accuracy of receiving data.
Response to Arguments
Applicant's arguments filed 03.18/2026 have been fully considered but they are not persuasive.
Applicant’s Argument 1
Claim 1 has been amended to recite "wherein the first set of correlators and the second set of correlators are configured to perform the search in parallel." Jones and HE fail to teach the newly amended claims.
Examiner’s Response 1
Examiner respectfully disagrees. Newly added reference Wang teach wherein the first set of correlators and the second set of correlators are configured to perform the search in parallel in Fig. 3 “304”, [0033] “The logic implementation 300, for example, includes a logic section 302 that compares a template pattern (tm[i]) for the MP for which the destination is searching against the input bits (in[i]). The XOR logic 304 finds mismatches between the template and the input bits, (XOR) (Examienr’s Note: XOR logic 304 could be broadly be interpreted as a correlator since the XOR are used to perform searching for mismatch” and there multiple xor logic 304 being performed in parallel”.
Furthermore Wang shows sequential checks occurring after the “parallel correlator” in Fig. 10.
Applicant’s Argument 2
Claims 10-15 stand rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of He, and further in view of Jones 2 (US 10,320,516).
Claim 10 has been amended to recite "wherein the first correlator circuit and the second correlator circuit are configured to perform the search in parallel."
Examiner’s Response 2
Examiner respectfully disagrees. See above for similar reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Shiue US6590872 teaches parallel correlator.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/K.T.F./Examiner, Art Unit 2411
/DERRICK W FERRIS/Supervisory Patent Examiner, Art Unit 2411
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