DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 1a in the reply filed on 9 June 2026 is acknowledged. The traversal is on the ground(s) that there is no search burden for Species 1a-1c. This is not found persuasive. It is the Examiner’s position that a search for the features of Species 1a, i.e. a single memory stack, would not necessarily yield prior art applicable to a device with two memory stacks which are features of Species 1b and 1c, since different search strategies, classification symbols, and keywords would have to be employed. Similarly, a search for the features of Species 1b, i.e. a device with two memory stacks and digital device layers where the bridge die couples the digital device layers through the interfaces of the digital device layers, would not necessarily yield prior art applicable to Species 1c, and vice versa. While Species 1c is drawn to a similar device with two memory stacks, the coupling of the compute modules are through interposers, rather than directly through the interface. As disclosed, these species each have mutually exclusive features. Thus, the independent and distinct species outlined in Species Group I would each require a different field of search, imposing an undue search burden on the Examiner if the election between the species of Species Group I was not required.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the Examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Applicant further elected Species 2a without traverse in the reply filed on 9 June 2026.
The requirement is still deemed proper and is therefore made final. The claims are restricted to the elected Species 1a and 2a and the embodiment including features of both elected species. Claims 12 and 17-20 are not drawn to the elected species and are withdrawn from consideration. Claims 1-11 and 13-16 are examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10 and 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dokania et al. (“Dokania” US 2023/0059491).
Regarding claim 1, Dokania discloses an integrated circuit (IC) die stack (Figure 4B), comprising:
a digital device layer (compute die 402, which contains logic devices/processors, para. [0084], i.e. digital device layers) having a memory interface (since the digital device layer 402 is a processor connected to a memory chip 403, the digital device layer would have a memory interface to communicate with the memory device, see para. [0089] and also [0097]-[0099] which discloses various components of the compute die 402);
a cooling solution (315) on a first side (upper side) of the digital device layer (402, see Figure 4B); and
a plurality of memory layers (DRAM dies 4031-N) on a second side (lower side) of the digital device layer (402) opposite the first side thereof (see Figure 4B, the memory layers 4031-N are on the lower side of the digital device layer, opposite the top side).
Regarding claim 2, Dokania further discloses a package substrate (301) attached to an opposite side of the plurality of memory layers (4031-N) attached to the digital device layer (402, Figure 4B shows the package substrate being on the lower side of the memory layers 4031-N, opposite the top side attached to the digital device layer 402).
Regarding claim 3, Dokania discloses wherein the digital device layer (402) and the plurality of memory layers (4031-N) are electrically interconnected (para. [0089]).
Regarding claim 4, Dokania discloses wherein the digital device layer (402) and the plurality of memory layers (4031-N) are electrically interconnected with through-silicon vias (TSVs) (see para. [0089]).
Regarding claim 5, Dokania discloses wherein the TSVs (para. [0089]) are adapted for coupling to external connections on the package substrate (C4 bumps, see Figure 4B).
Regarding claim 6, Dokania discloses wherein the external connections (C4) are adapted for coupling to power, ground, and input-output and control signals (see para. [0089]).
Regarding claim 7, Dokania discloses wherein the digital device layer (402) is selected from the group consisting of any one or a combination of a microcontroller, a microprocessor, a mixed signal processor, a central processing unit (CPU), a programmable logic array (PLA), an application specific integrated circuit (ASIC), a digital signal processor (DSP), a graphics processing unit (GPU), a field programmable gate array (FPGA), neural processing unit and tensor processing unit (see para. [0084]).
Regarding claim 8, Dokania discloses wherein the plurality of memory layers (4031-N) are selected from the group consisting of dynamic random-access memory (DRAM), static random-access memory (SRAM), serial shift registers, eDRAM, Flash, phase-change memory, resistive RAM, ferromagnetic RAM and spin-torque transfer RAM (DRAM dies, see Figure 4B, para. [0089]).
Regarding claim 9, Dokania discloses wherein the cooling solution (315) is a thermal dissipation device with heat transfer enhancement structures selected from the group consisting of a heat sink, a heat sink with fins, liquid cooling tubes, vapor chambers, heat pipes, and cold plates (heat sink with fins, see Figure 4B).
Regarding claim 10, Dokania further discloses through- mold/through-dielectric vias (TDVs) (see para. [0084], which discloses that the logic/processor of the compute die is embedded in a dielectric material, thus TDVs must be present in order to vertically electrically connect the processor to other electrical connections in the package, such as the TSVs which electrically connect the compute die to the substrate, see para. [0089]) adapted for coupling power, ground, and input-out and control signals directly between the digital device layer and the package substrate (see para. [0089]).
Regarding claim 13, Dokania discloses wherein the digital device layer (402) comprises a plurality of compute modules (see Figure 7A, para. [0099]), wherein at least one of the plurality of compute modules has a memory interface (see claim 1, para. [0097]-[0099]).
Regarding claim 14, Dokania further discloses an active interposer layer (controller die 401, see Figure 4B) between the plurality of compute modules (402) and the plurality of memory layers (4031-N, see Figure 4B).
Regarding claim 15, Dokania further discloses a logic layer electrically coupled to the digital device layer (402, see para. [0083], [0097]-[0099]).
Regarding claim 16, Dokania discloses wherein metal pads (micro-bumps, see Figure 4B) between the plurality of memory layers (4031-N) are coupled together using hybrid-bonding (para. [0079]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Dokania as applied to claim 10 above, and further in view of Liu et al. (“Liu” US 2020/0286847).
Regarding claim 11, Dokania does not explicitly disclose a passive silicon die coupled directly to the digital device layer and to the package substrate through TDVs.
Liu discloses, however, a passive silicon die (bridge die 110B) coupled directly to the digital device layer (logic die, 102B) and to the package substrate (106) through TDVs (see vias through mold/dielectric material connecting the logic die to the substrate in Figure 1).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Liu into the teachings of Dokania to include the passive silicon die as claimed for the purpose of providing high density electrical interconnections (Liu, para [0003]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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