DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/15/2023 was filed and is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the features must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
“a first direction parallel to a lower surface of the substrate”, as recited in claim 10, is not shown in any figure.
“a capacitor including a lower electrode, a dielectric layer, and an upper electrode”, as recited in claim 18, is not shown in any figure.
“the inner word line crosses each outer active pattern of the plurality of outer active patterns”, as recited in claim 12, is not shown in any figure.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to
several views of the drawings for consistency. Additional replacement sheets may be necessary
to show the renumbering of the remaining figures. Each drawing sheet submitted after the
filing date of an application must be labeled in the top margin as either "Replacement Sheet" or
"New Sheet" pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the
applicant will be notified and informed of any required corrective action in the next Office
action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 13 recites in lines 15-16 “the outer bit line is electrically connected to one of the pair of outer source/drain regions” and recites in lines 17-18 “the inner bit line is electrically connected to one of the pair of inner source/drain regions”. As shown in Fig. 4A, the inner/outer bit lines are connected to an inner/outer source/drain region and not to a pair of source/drain regions. It is suggested the applicant change “one of the pair of outer source/drain regions” to “an outer source drain region”, and change “one of the pair of inner source/drain regions” to “an inner source drain region”.
Claim 14 recites in lines 1-2 “the outer data storage pattern is electrically connected to the other one of the pair of outer source/drain regions” and recites in lines 3-4 “the inner data storage pattern is electrically connected to the other one of the pair of inner source/drain regions”. As shown in Fig. 4A, inner/outer data storage patterns are connected to the other inner/outer source/drain region and not to a pair of source/drain regions. It is suggested the applicant change “to the other one of the pair of outer source/drain regions” to “the other outer source drain region”, and change “to the other one of the pair of inner source/drain regions” to “the other inner source drain region”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999).
Claims 1 and 13, line 2, both recite the term "crossing", referring to a trench “crossing” the outer active pattern, and the term is used in the claims to mean "passing over" or "traversing" or "traveling across" or "intersecting" while the accepted meaning and use in semiconductor technology is “in”. Generally, a trench is “in” an outer active pattern, instead of “crossing” an outer active pattern. The term “crossing” is indefinite because the specification does not clearly redefine the term. Specifically, one of ordinary skill in the art understands “crossing” refers to “in”. However, what is disclosed by the applicant bears no resemblance to “in”. For the purpose of examination, the Examiner interprets the term as “in”.
Claim 15, lines 1-3, recites "the inner bit line and the inner data storage pattern are interposed between the outer active pattern and the outer data storage pattern". However, contrary to this recitation, the outer active pattern surrounds the inner bit line and the inner data storage pattern, and as such, it is not located only on one side of the inner bit line and the inner data storage pattern. It is suggested the applicant change the limitation to “the inner bit line and the inner data storage pattern are interposed between the outer bit line and the outer data storage pattern" for clarification and definiteness.
Claim 3, lines 1-3, recites “a thickness of the separation insulating pattern is greater than or substantially equal to both a thickness of the outer dielectric pattern and a thickness of the inner dielectric pattern, respectively”, and Claim 19, lines 16-18, recites “a thickness of the separation insulating pattern is greater than or substantially equal to a thickness of the first dielectric pattern and a thickness of the second dielectric pattern, respectively”. It is not clear whether a thickness of the separation insulating pattern is greater than or substantially equal to the summation of a thickness of the dielectric patterns or either of them. Specifically, the use of the words “both” and “respectively” is not clear. The specification does not appear to further clarify the limitation. Therefore, it is suggested the applicant change the limitation in claim 3 to “a thickness of the separation insulating pattern is greater than or substantially equal to each of a thickness of the outer dielectric pattern and a thickness of the inner dielectric pattern”, and in claim 19 it is suggested the applicant change the limitation to “a thickness of the separation insulating pattern is greater than or substantially equal to each of a thickness of the first dielectric pattern and a thickness of the second dielectric pattern”, or a similar phrase to clarify and for definiteness. For the purpose of examination, the examiner interprets “a thickness of the separation insulating pattern is greater than or equal to either a thickness of the outer dielectric pattern or a thickness of the inner dielectric pattern” in claim 3, and in claim 19, as “a thickness of the separation insulating pattern is greater than or equal to either a thickness of the first dielectric pattern or a thickness of the second dielectric pattern”.
Claim 12, lines 1-2, recites “the inner word line crosses each outer active pattern of the plurality of outer active patterns”. However, the inner word line is surrounded by the inner active pattern which is separated from the outer active pattern by the separation insulation pattern, and as such, the inner word line cannot cross the outer active patterns. The specification does not appear to further clarify the limitation. Therefore, it is suggested the applicant change the limitation to “the inner word line crosses each inner active pattern of the plurality of inner active patterns.". For the purpose of examination, the Examiner interprets the term as “the inner word line crosses each inner active pattern of the plurality of inner active patterns”.
Claim 19, lines 16-18, recites “a thickness of the separation insulating pattern is greater than or substantially equal to a thickness of the first dielectric pattern and a thickness of the second dielectric pattern, respectively”. The relative term “substantially” renders the claims indefinite. It is suggested the applicant remove the relative term “substantially” from the claim.
Dependent claims 2, 4-11, 14, 16-18, and 20 are also rejected due to dependencies on claims 1, 13, and 19.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claims 1-9, 11-12, and 19-20, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Zhao (US 11527633 B2, hereinafter Zhao) in view of Lee et al. (US 2023/0232614 A1, hereinafter Lee).
Regarding claim 1, Zhao teaches in Fig. 1 a semiconductor device comprising:
an outer active pattern (epitaxial layer 18) on a substrate (11),
the outer active pattern (18) having a trench (outer surface of 12) crossing the outer active pattern (18, the outer surface of 12 is in epitaxial layer 18),
an outer word line (polysilicon gate 13/ gate dielectric 12) covering a wall of the trench (outer surface of 12),
an inner active pattern (auxiliary polysilicon layer 15) covering the outer word line (13/12) in the trench (outer surface of 12),
a separation insulating pattern (14) interposed between the outer word line (13/12) and the inner active pattern (15) in the trench (outer surface of 12),
wherein the outer word line (13/12) includes an outer gate electrode (13) between the outer active pattern (18) and the separation insulating pattern (14),
and an outer dielectric pattern (12) between the outer gate electrode (13) and the outer active pattern (18),
wherein the outer active pattern (18) is spaced apart from the outer gate electrode (13) with the outer dielectric pattern (12) therebetween, and
Zhao does not explicitly teach:
1) an inner word line covering the inner active pattern (15) in the trench (outer surface of 12); and
2) wherein the outer word line (13/12) and the inner word line are insulated from each other (by layer 14 as shown in Fig. 1); and
3) wherein the inner word line includes an inner gate electrode covering the inner active pattern (15) in the trench (outer surface of 12) and an inner dielectric pattern between the inner gate electrode and the inner active pattern (15); and
4) wherein the inner active pattern (15) is spaced apart from the inner gate electrode with the inner dielectric pattern interposed therebetween.
Lee teaches in Fig. 2 and related text an inner gate structure (i.e. an inner word line; 40a and 40b including a gate electrode 44 and a gate dielectric 42).
Zhao and Lee are analogous art to the claimed invention because they are directed to semiconductor devices with trenched transistors with inner and outer active patterns and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zhao in view of Lee because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to include an inner gate structure (i.e. an inner word line including an inner gate electrode and an inner gate dielectric), as taught by Lee, in the auxiliary polysilicon layer of Zhao’s device, in order to have: 1) an inner word line covering the inner active pattern in the trench; and 2) wherein the outer word line and the inner word line are insulated from each other; and 3) wherein the inner word line includes an inner gate electrode covering the inner active pattern in the trench and an inner dielectric pattern between the inner gate electrode and the inner active pattern; and 4) wherein the inner active pattern is spaced apart from the inner gate electrode with the inner dielectric pattern interposed therebetween, with the motivation of creating a multi-gate semiconductor device with improved electrical characteristics which will also save space on the device substrate.
Regarding claim 2, Zhao in view of Lee teaches the semiconductor device of claim 1. Zhao further teaches wherein the separation insulating pattern separates the outer word line (13/12) from the inner active pattern (15).
Regarding claim 3, Zhao in view of Lee teaches the semiconductor device of claim 1.
Zhao does not explicitly teach wherein a thickness of the separation insulating pattern (14) is greater than or substantially equal to both a thickness of the outer dielectric pattern (12) and a thickness of the inner dielectric pattern, respectively.
Lee teaches in Fig. 2 that a thickness of a separation insulting layer (isolation layer 25) is thicker than gate dielectric (42) as it is shown in Fig. 2, the dielectric layer (42) is inside the isolation layer.
Zhao and Lee are analogous art to the claimed invention because they are directed to semiconductor devices with trenched transistors with inner and outer active patterns and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zhao in view of Lee because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to create the separation insulting layer, in order to make the thickness of the separation insulting layer greater than the thickness of each of the inner and outer dielectric patterns, as taught by Lee, in Zhao’s device, with the motivation of effectively insulating the outer word line and the inner active pattern.
Furthermore, with regard to the claimed ranges of thicknesses, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1980). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Regarding claim 4, Zhao in view of Lee teaches the semiconductor device of claim 1. Zhao further teaches that insulating pattern (14) includes an insulating material (col. 5, lines 65-67, the material of the intermediate dielectric layer is an oxide, or a non-conductive ceramic material).
Regarding claim 5, Zhao in view of Lee teaches the semiconductor device of claim 1.
Zhao further teaches wherein the outer active pattern (18) includes a pair of outer source/drain regions (16) thereon.
Zhao does not explicitly teach wherein the inner active pattern includes a pair of inner source/drain regions thereon.
Lee teaches in Fig. 2 and related text inner source/drain regions (SD1, SD2, and SD3).
Zhao and Lee are analogous art to the claimed invention because they are directed to semiconductor devices with trenched transistors with inner and outer active patterns and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zhao in view of Lee because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to include inner source/drain regions, as taught by Lee, in the auxiliary polysilicon layer of Zhao’s device, in order to have the inner active pattern include a pair of inner source/drain regions, with the motivation of creating a highly integrated semiconductor device with multiple source/drain regions.
Regarding claim 6, Zhao in view of Lee teaches the semiconductor device of claim 5.
Zhao does not explicitly teach wherein the outer active pattern further includes an outer channel region extending along the wall between the pair of outer source/drain regions, and wherein the inner active pattern further includes an inner channel region extending along the separation insulating pattern between the pair of inner source/drain regions.
Lee teaches in Fig. 2 and related text a channel region (CH1 and CH2).
Zhao and Lee are analogous art to the claimed invention because they are directed to semiconductor devices with trenched transistors with inner and outer active patterns and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zhao in view of Lee because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to include a channel region, as taught by Lee, in the epitaxial layer and in the auxiliary polysilicon layer of Zhao’s device, in order to have the outer active pattern further include an outer channel region extending along the wall between the pair of outer source/drain regions, and wherein the inner active pattern further includes an inner channel region extending along the separation insulating pattern between the pair of inner source/drain regions, with the motivation of creating a semiconductor device with channel regions to provide a path for the electrical current between the source/drain regions in the inner active pattern and in the outer active pattern.
Regarding claim 7, Zhao in view of Lee teaches the semiconductor device of claim 5.
Zhao does not explicitly teach wherein the pair of inner source/drain regions are interposed between the pair of outer source/drain regions.
However, as mentioned in the rejection of claim 5, Zhao teaches outer source/drain regions in the outer active pattern and Lee teaches in Fig. 2 and related text inner source/drain regions (SD1, SD2, and SD3) in the inner active pattern.
Zhao and Lee are analogous art to the claimed invention because they are directed to semiconductor devices with trenched transistors with inner and outer active patterns and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zhao in view of Lee because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to have the pair of inner source/drain regions (Lee, SD) be interposed between the pair of outer source/drain regions in Zhao (16), with the motivation of realizing an efficient and compact device.
Regarding claim 8, Zhao in view of Lee teaches the semiconductor device of claim 1.
Zhao further teaches that the inner active pattern (15) includes a semiconductor material (Fig. 1; auxiliary polysilicon layer).
Regarding claim 9, Zhao in view of Lee teaches the semiconductor device of claim 1.
Zhao teaches that the outer active pattern (18) surrounds the outer word line (13/12) in the trench (outer surface of 12), and
wherein the inner active pattern (15) surrounds the inner word line in the trench (outer surface of 12).
Regarding claim 11, Zhao in view of Lee teaches the semiconductor device of claim 1.
Zhao does not explicitly teach a plurality of outer active patterns, and wherein the outer word line crosses each outer active pattern of the plurality of outer active patterns.
Lee teaches in Fig. 1 plurality of outer active patterns (Fig. 1; active regions 10), and wherein the outer word line (Fig. 1; 40c and 40d) crosses each outer active pattern of the plurality of outer active patterns (10).
Zhao and Lee are analogous art to the claimed invention because they are directed to semiconductor devices with trenched transistors with inner and outer active patterns and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zhao in view of Lee because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to create outer active patterns and place the outer word line, as taught by Lee, in Zhao’s device, in order to have a plurality of outer active patterns, and wherein the outer word line crosses each outer active pattern of the plurality of outer active patterns, with the motivation of realizing an efficient and compact claimed device.
Regarding claim 12, Zhao in view of Lee teaches the semiconductor device of claim 11.
Zhao does not explicitly teach wherein the inner word line crosses each outer active pattern of the plurality of outer active patterns.
Lee teaches in Fig. 1 that the semiconductor device of claim 11, wherein the inner word line (Fig.1; 40a and 40b) crosses each inner active pattern of the plurality of inner active patterns (Fig.1; active regions 10a).
Zhao and Lee are analogous art to the claimed invention because they are directed to semiconductor devices with trenched transistors with inner and outer active patterns and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zhao in view of Lee because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to position the inner word line to cross the inner active pattern, as taught by Lee, in Zhao’s device, in order to have the inner word line cross each inner active pattern of the plurality of inner active patterns, with the motivation that Lee shows in Figure 1, this arrangement is common for an operational semiconductor memory device.
Regarding claim 19, Zhao teaches in Fig. 1 a semiconductor device comprising:
a second active pattern (15) on the first active pattern (18),
a separation insulating pattern (14) between the first active pattern (18) and the second active pattern (15);
a first word line (13/12) between the first active pattern (18) and the separation insulating pattern (14); and
wherein the first word line includes (12/13) a first gate electrode (13) between the first active pattern (18) and the separation insulating pattern (14), and a first dielectric pattern (12) between the first active pattern (18) and the first gate electrode (13),
Zhao does not explicitly teach:
a second word line on the second active pattern (15),
wherein the first word line (13/12) and the second word line are insulated from each other (by layer 14 as shown in Fig. 1),
wherein the second word line includes a second gate electrode (inside 15) on the second active pattern (15) and a second dielectric pattern between the second active pattern (15) and the second gate electrode, and
wherein a thickness of the separation insulating pattern (14) is greater than or substantially equal to a thickness of the first dielectric pattern (12) and a thickness of the second dielectric pattern (inside 15), respectively.
Lee teaches in Fig. 2 and related text an inner gate structure (i.e. an inner word line; 40a and 40b including a gate electrode 44 and a gate dielectric 42). Lee further teaches in Fig. 2 that a thickness of a separation insulting layer (isolation layer 25) is thicker than gate dielectric (42) as it is shown in Fig. 2, the dielectric layer (42) is inside the isolation layer.
Zhao and Lee are analogous art to the claimed invention because they are directed to semiconductor devices with trenched transistors with inner and outer active patterns and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zhao in view of Lee because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to include an inner gate structure (i.e. an inner word line including an inner gate electrode and an inner gate dielectric), as taught by Lee, in the auxiliary polysilicon layer of Zhao’s device, and make the insulting layer thicker than the gate dielectrics, as taught by Lee, in Zhao’s device, in order to have: 1) a second word line on the second active pattern; and 2) wherein the first word line and the second word line are insulated from each other; and 3) wherein the second word line includes a second gate electrode on the second active pattern and a second dielectric pattern between the second active pattern and the second gate electrode; and 4) wherein a thickness of the separation insulating pattern is greater than or substantially equal to a thickness of the first dielectric pattern and a thickness of the second dielectric pattern, respectively, with the motivation of creating a multi-gate semiconductor device with improved electrical characteristics which will also save space on the device substrate.
Regarding claim 20, Zhao in view of Lee teaches the semiconductor device of claim 19. Zhao further teaches in Fig. 1 that the separation insulating pattern (14) separates the first word line (13/12) from the second active pattern (15).
Claims 10 and 13-18, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Zhao (US 11527633 B2, hereinafter Zhao) in view of Lee et al. (US 2023/0232614 A1, hereinafter Lee), and further in view of Kim et al. (US 20230422487 A1, hereinafter Kim).
Regarding claim 10, Zhao in view of Lee teaches the semiconductor device of claim 1.
Zhao in view of Lee does not explicitly teach
wherein the outer active pattern extends in a first direction parallel to a lower surface of the substrate,
wherein the outer word line extends in a second direction parallel to the lower surface of the substrate, and
wherein an angle between the first direction and the second direction is greater than 0 and less than or equal to 90°.
Kim teaches in Fig. 2 and related text wherein the outer active pattern extends in a first direction parallel to a lower surface of the substrate ([0028]; lines 1-4, Each of the active patterns AP elongated in a third direction D3. The third direction D3 may be parallel to the lower surface of the substrate), wherein the outer word line extends in a second direction parallel to the lower surface of the substrate ([0030]; line 3, The word lines WL may extend in the second direction D2; [0027]; lines 7-8, the second direction D2 may be parallel to a lower surface of the substrate 100.), and wherein an angle between the first direction and the second direction is greater than 0 and less than or equal to 90° (as shown in Kim Fig. 2, the angle between the direction D3 and direction D2 is greater than 0 and less than or equal to 90°).
Zhao, Lee and Kim are analogous art to the claimed invention because they are directed to semiconductor devices with trenched transistors with inner and outer active patterns and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of Zhao and Lee in view of Kim because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to place the outer active patterns and the outer word line, as taught by Kim, in the device of Zhao and Lee, in order to have the outer active pattern extend in a first direction parallel to a lower surface of the substrate, wherein the outer word line extends in a second direction parallel to the lower surface of the substrate, and wherein an angle between the first direction and the second direction is greater than 0 and less than or equal to 90°, with the motivation that Kim teaches it is well known to have an angle between the outer active pattern and the outer word line (Kim, [0027]-[0030]).
Furthermore, Figure 2 in Kim illustrates the angle (between D2 and D3) being greater than 0 and less than or equal to 90 and although the drawings are not to scale, they may be relied upon for what they would reasonably teach or convey to one of ordinary skill in the art when interpreted in view of the specification (MPEP 2125(II)), In re Wright, 569 F.2d 1124, 1127-28, 193 USPQ 332, 335-36 (CCPA 1977)).
Regarding claim 13, Zhao teaches in Fig. 1 a semiconductor device comprising:
an outer active pattern (epitaxial layer 18) on a substrate (11),
the outer active pattern (18) having a trench (outer surface of 12) crossing the outer active pattern (18, the outer surface of 12 is in epitaxial layer 18),
an outer word line (polysilicon gate 13/ gate dielectric 12) covering a wall of the trench (outer surface of 12),
an inner active pattern (auxiliary polysilicon layer 15) covering the outer word line (13/12) in the trench (outer surface of 12),
a separation insulating pattern (14) interposed between the outer word line (13/12) and the inner active pattern (15) in the trench (outer surface of 12),
Zhao does not explicitly teach:
an inner word line covering the inner active pattern (15) in the trench (outer surface of 12);
an outer bit line and an outer data storage pattern electrically connected to the outer active pattern, respectively;
an inner bit line and an inner data storage pattern electrically connected to the inner active pattern (15), respectively,
wherein the inner active pattern (15) includes a pair of inner source/drain regions thereon,
5) wherein the outer bit line is electrically connected to one of the pair of outer source/drain regions (16), and
6) wherein the inner bit line is electrically connected to one of the pair of inner source/drain regions.
Lee teaches in Fig. 2 and related text an inner gate structure (i.e. an inner word line; 40a and 40b including a gate electrode 44 and a gate dielectric 42). Lee further teaches in Fig. 2 and related text inner source/drain regions (SD1, SD2, and SD3).
Further, Kim teaches in Fig. 6 and related text bit lines (BL) and data storage patterns (DSP). As shown in Fig. 6, data storage pattern (DSP) is connected to second impurity region 112. Second impurity regions 112 may be provided in the active patterns AP ([0029]; lines 1-2). The bit line contacts DC may be interposed between the active patterns AP and the bit lines BL ([0034]; lines 6-8).
Zhao, Lee and Kim are analogous art to the claimed invention because they are directed to semiconductor devices with trenched transistors with inner and outer active patterns and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zhao in view of Lee and further in view of Kim because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to include an inner gate structure (i.e. an inner word line including an inner gate electrode and an inner gate dielectric) and inner source/drain regions , as taught by Lee, in the auxiliary polysilicon layer of Zhao’s device, and also to include inner/outer word lines and inner/outer data storage patterns in the inner and outer active patterns, as taught by Kim, in Zhao’s device, in order to have: 1) an inner word line covering the inner active pattern in the trench; and 2) an outer bit line and an outer data storage pattern electrically connected to the outer active pattern, respectively; and 3) an inner bit line and an inner data storage pattern electrically connected to the inner active pattern, respectively; and 4) wherein the inner active pattern includes a pair of inner source/drain regions thereon; and 5) wherein the outer bit line is electrically connected to one of the pair of outer source/drain regions; and 6) wherein the inner bit line is electrically connected to one of the pair of inner source/drain regions, with the motivation of creating a highly-integrated semiconductor memory device including the necessary components.
Regarding claim 14, Zhao in view of Lee and Kim teaches the semiconductor device of claim 13.
Zhao in view of Lee does not explicitly teach wherein the outer data storage pattern is electrically connected to the other one of the pair of outer source/drain regions, and wherein the inner data storage pattern is electrically connected to the other one of the pair of inner source/drain regions.
Kim further teaches in Fig. 6 and in [0059]; lines 3-4, the storage node contact BC may be electrically connected to the second impurity region 112.
Zhao, Lee and Kim are analogous art to the claimed invention because they are directed to semiconductor devices with trenched transistors with inner and outer active patterns and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zhao in view of Lee further in view of Kim because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to connect the data storage patterns to the source/drain regions in the active patterns, as taught by Kim, wherein the outer data storage pattern is electrically connected to the other one of the pair of outer source/drain regions, and wherein the inner data storage pattern is electrically connected to the other one of the pair of inner source/drain regions with the motivation of creating a highly-integrated semiconductor memory device including the necessary connections.
Regarding claim 15, Zhao in view of Lee and Kim teaches the semiconductor device of claim 13.
Zhao in view of Lee does not explicitly teach wherein the inner bit line and the inner data storage pattern are interposed between the outer active pattern and the outer data storage pattern.
However, Zhao teaches an outer active pattern surrounding an inner active pattern. Further, Kim teaches an inner bit line and an inner data storage pattern in the inner active pattern and outer data storage pattern in the outer active pattern.
Zhao, Lee and Kim are analogous art to the claimed invention because they are directed to semiconductor devices with trenched transistors with inner and outer active patterns and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zhao in view of Lee further in view of Kim because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to have the inner bit line and the inner data storage pattern be interposed between the outer active pattern and the outer data storage pattern in Zhao’s device, as taught by Kim, with the motivation of realizing an efficient and compact device.
Regarding claim 16, Zhao in view of Lee and Kim teaches the semiconductor device of claim 15.
Zhao does not explicitly teach wherein the inner bit line is interposed between the outer bit line and the inner data storage pattern.
However, Kim teaches an inner bit line and an inner data storage pattern in the inner active pattern and outer bit line in the outer active pattern. It should be noted that no order is specified in Kim’s teaching for connecting the inner bit line and the inner data storage patten to the inner active region as both impurity regions 111 and 112 having the same the conductivity type ([0029]; lines 7-9, The first impurity regions 111 may include impurities of the same conductivity type (e.g., N-type) as those of the second impurity regions 112.).
Zhao, Lee and Kim are analogous art to the claimed invention because they are directed to semiconductor devices with trenched transistors with inner and outer active patterns and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zhao in view of Lee further in view of Kim because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to have the inner bit line be interposed between the outer bit line and the inner data storage pattern, in Zhao’s device, as taught by Kim, with the motivation of realizing an efficient and compact device.
Regarding claim 17, Zhao in view of Lee and Kim teaches the semiconductor device of claim 15.
Zhao in view of Lee does not explicitly teach wherein the inner data storage pattern is interposed between the outer bit line and the inner bit line.
Kim further teaches wherein the inner data storage pattern is interposed between the outer bit line and the inner bit line (Claim1; storage node contacts interposed between adjacent bit lines).
Zhao, Lee and Kim are analogous art to the claimed invention because they are directed to semiconductor devices with trenched transistors with inner and outer active patterns and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zhao in view of Lee because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to have the inner data storage pattern be interposed between the outer bit line and the inner bit line, in Zhao’s device, as taught by Kim, with the motivation of realizing an efficient and compact device.
Regarding claim 18, Zhao in view of Lee and Kim teaches the semiconductor device of claim 13.
Zhao in view of Lee does not explicitly teach wherein each of the outer data storage pattern and the inner data storage pattern is a capacitor including a lower electrode, a dielectric layer, and an upper electrode.
Kim further teaches wherein each of the outer data storage pattern and the inner data storage pattern is a capacitor including a lower electrode, a dielectric layer, and an upper electrode (([0065], lines 1-3, The data storage pattern DSP may be, for example, a capacitor including a lower electrode, a dielectric layer, and an upper electrode.).
Zhao, Lee and Kim are analogous art to the claimed invention because they are directed to semiconductor devices with trenched transistors with inner and outer active patterns and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zhao in view of Lee further in view of Kim because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to include a capacitor for each of the outer data storage pattern and the inner data storage pattern, in Zhao’s device, as taught by Kim, with the motivation of realizing an efficient and compact device.
Conclusion
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/H.N./Examiner, Art Unit 2811
/LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811
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