DETAILED ACTION
This action is responsive to the amendments filed November 25, 2025. Claims 1-20 are pending. Claims 1-2, 4, 8-9, 11, 14-15, and 17 have been amended. Claims 1, 8, and 14 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The amendments to the drawings for Figures 1A, 1B, 2, 3, 4, 5A, 5B, 7A, 7B, 7C, 7D, 8A, 8B, 8C, 9A, 9B, 9C, 9D, 9E, 10A, 10B, 10C, 10D, 10E, 10F, 10G, 11A, 11B, and 11C are acknowledged and accepted. The prior objection to the drawings regarding labeling as prior art has been withdrawn.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Amended claims 1, 8, and 14 recite: "the application of the select gate voltage to the at least one source-side select gate transistor throughout an entire duration of the plurality of subsequent erase verify iterations for the at least some of the memory cells", which appears to be directed primarily toward Figs. 17 & 18. As necessitated by the amendment and based on a new understanding of the facts, none of the figures depict that limitation. At best, the waveform of the SGS voltage illustrated in Figs. 17 & 18 depict a "pedestal profile" characterized by a delayed-assertion relative to the start of the first subsequent erase verify iteration, spanning the interstitial iterations, and an early-termination relative to the concluding iteration, rather than throughout an entire duration.
Therefore, "the application of the select gate voltage to the at least one source-side select gate transistor throughout an entire duration of the plurality of subsequent erase verify iterations for the at least some of the memory cells" must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 11 is objected to because of the following informalities: On pg. 10 of Claims filed November 25, 2025, amended claim 11 has a status identifier of "(Original)" but should have the status identifier of "(Currently Amended)". As per 37 CFR 1.121(c), every claim in a claim listing must be followed by a parenthetical expression indicating its current status. Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Such limitations are as recited in claims 2-7 for example (e.g., “the control means (is further) configured to”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 8, 10, 14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Dutta et al. (US 9343160; “Dutta” – of Record) in view of Tokiwa (US 20210020250 – of Record) and further in view of Lien et al (US 11335411; "Lien").
Regarding independent claims 1, 8, and 14, Dutta discloses a memory apparatus, a controller in communication with a memory apparatus, and a method of operating a memory apparatus, respectively, comprising:
memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage and disposed in memory holes each defining a channel (Fig. 1A. & Fig. 10C),
the memory holes grouped into a plurality of strings (col. 1, ln. 36-44; "ultra high density storage devices have been proposed using a 3D stacked memory structure having strings of memory cells. One such storage device is sometimes referred to as a Bit Cost Scalable (BiCS) architecture. For example, a 3D NAND stacked memory device can be formed from an array of alternating conductor and insulator layers. A memory hole is drilled in the layers to define many memory layers simultaneously. A NAND string is then formed by filling the memory hole with appropriate materials");
and a control means coupled to the plurality of word lines and configured to (Fig. 5B: control circuitry 510):
apply at least one erase pulse to the channel of the memory holes of all of the plurality of strings (Fig. 8A. See also col. 15, ln. 17-20; "the system applies the erase pulse, along with other erase conditions to the group of NAND strings being erased"),
and apply an erase verify voltage to the plurality of word lines and successively determine whether at least some of the memory cells of ones of the plurality of strings being erased have the threshold voltage below the erase verify voltage in a plurality of subsequent erase verify iterations (Fig. 11A & Fig. 11B where it illustrates the process of erase verify and potential successive erase loops (B). It is also observed that step 1076 determines the validity of the erase threshold voltage),
Dutta is silent with respect to the explicit voltage characteristics of the word line and the source-side select gate transistor during the erase verify iterations.
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However, Tokiwa teaches and apply a select gate voltage to at least one source-side select gate transistor (Fig. 14 where it illustrates the application of a select gate voltage to SGS during an erase verify operation)
the application of the erase verify voltage to the plurality of word lines maintained constantly throughout an entire duration of the plurality of subsequent erase verify iterations for the at least some of the memory cells (Fig. 14 where it illustrates during the erase verify operation of at least strings Str0-Str1, word lines (Wli) are held at the erase verify voltage throughout the duration of the operation. See also para. 70; "the word line WL is connected to the signal CG line. In other words, the potential of the signal CG line CG (the erase verify voltage Vevfy) continues to be transferred. Thus, the discharge and recharge of the word line WL will be unnecessary for the erase verify of the subsequent string Str1").
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Dutta and Tokiwa are silent with respect to the profile duration of the voltage on the source-side select gate transistor during the erase verify.
However, Lien teaches and the application of the select gate voltage to the at least one source-side select gate transistor throughout an entire duration of the plurality of subsequent erase verify iterations for the at least some of the memory cells (Fig. 17. Also see Examiner's Markup above. It is noted that Lien's erase verify iteration of odd and even sub-blocks is also analogous to that of the instant application).
Dutta, Tokiwa and Lien are from the same field of endeavor as applicant’s invention directed to the erase verify operation of 3D non-volatile memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Dutta’s multi-level erase verify process with the teachings of Tokiwa’s word line control during the erase verify operation and with Lien's holding the SGS line active. Doing so would result in the reduction of power consumption as well as increased speed during the erase verify operation in a 3D non-volatile memory device.
Regarding claims 3, 10, and 16, Dutta, Tokiwa and Lien combined disclose the limitations of claims 1, 8, and 14 respectively.
As applied, Dutta further discloses wherein the control means/controller/method is further configured to:
apply the erase verify voltage to the plurality of word lines and determine whether the memory cells of each of the plurality of strings have the threshold voltage below the erase verify voltage in each of the plurality of subsequent erase verify iterations (Fig. 8C: steps 872 through 876);
return to apply the at least one erase pulse to the channel of the memory holes of all of the plurality of strings in response to the memory cells of one of the plurality of strings not having the threshold voltage below the erase verify voltage in one of the plurality of subsequent erase verify iterations (Fig. 8C: step 886 where it loops back to do another erase loop);
enter a low current consumption mode in response to the memory cells of a first one of the plurality of strings having the threshold voltage below the erase verify voltage in a first one of the plurality of subsequent erase verify iterations (Fig. 8C: step 880);
and set a status all of the plurality of strings as passing erase verify in response to the memory cells of a last one of the plurality of strings having the threshold voltage below the erase verify voltage a last one of the plurality of subsequent erase verify iterations (Fig. 8C: step 883).
Claims 2, 4, 9, 11, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Dutta et al. (US 9343160; “Dutta” – of Record) in view of Tokiwa (US 20210020250 – of Record) and further in view of Lien et al (US 11335411; "Lien") and further in view of Li et al. (US 20210335426; “Li1” – of Record) and further in view of Li et al. (US 11335419; “Li2” – of Record).
Regarding claims 2, 9, and 15, Dutta, Tokiwa and Lien combined disclose the limitations of claims 1, 8, and 14 respectively.
As applied, Dutta further discloses wherein
the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack (Fig. 10C. See also col. 20, ln. 20-22; "Columns of memory cells C0 to C11 are depicted in the multi-layer stack, having layers BG, WL0-WL6, BG, and D0-D8"),
the memory holes extend vertically through the stack (Fig. 10D. See also col. 21, ln. 14-15; "Each block includes rows of columnar, e.g., vertical, memory holes or pillars, represented by circles in FIG. 10D"),
the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and the at least one source-side select gate transistor on a source-side of each of the memory holes (Fig. 9A: SGD, SGS),
the drain-side select gate transistor of each of the memory holes is connected to one of a plurality of bit lines and the at least one source-side select gate transistor of each of the memory holes is connected to a source line (Fig. 9A where it illustrates the SGD transistor connected to bit lines BL0-BL2 and the SGS transistor connected to the source line through SE0-SE2),
the plurality of word lines including one or more dummy word lines adjacent at least one of the drain- side select gate transistor and the source-side select gate transistor (Fig. 3 WL0 and WL63. It is noted that the term "dummy word line" is defined in the instant application in para. 177 as "The plurality of word lines including one or more dummy word lines (e.g., word lines WLO and WL63 of FIG. 3) adjacent at least one of the drain-side select gate transistor and the at least one source-side select gate transistor". It is further noted that Dutta's Fig. 3 is identical to Fig. 3 in the instant application),
the at least some of the memory cells of ones of the plurality of strings being erased includes the memory cells of all of the plurality of word lines (Fig. 8C: step 872. See also col. 15, ln. 17-19; "In step 872, the system applies the erase pulse, along with other erase conditions to the group of NAND strings being erased"),
Dutta, Tokiwa and Lien are silent with respect to specific applications of select gate and dummy word line voltages during the reduced power erase verify operation.
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However, Li1 teaches and the control means/controller/method is further configured to alternately apply a select gate voltage and a steady state voltage VSS to the drain-side select gate transistor coupled to the memory cells (See Examiner's Markup and Fig. 6B. See also para. 27; "T1 is when a verification stage begins", "and T3 is when the verification stage ends". It is noted that Li's memory array structure has odd word lines (FIG. 2: WL1, WL3) and even word lines (FIG. 2: WL2, WL4)),
the application of the select gate voltage to the drain-side select gate transistor alternating from the select gate voltage to the steady state voltage VSS for each of the plurality of subsequent erase verify iterations (Id and for the same reasons),
the application of the select gate voltage causing the drain-side select gate transistor to be conductive and the application of the select gate voltage to the source-side select gate transistor causing the source-side select gate transistor to be conductive (It is well understood in the art that applying a select gate voltage to a select gate transistor of a NAND flash memory array necessarily causes the transistor to be conductive);
Li1 is silent with respect to specific word line voltages which may be considered “dummy word lines” although it is noted that the term “dummy word lines” in the instant application apparently applies to nominal data word lines which are merely designated so.
However, Li2 teaches and continuously apply a read pass voltage to the one or more dummy word lines for the entire duration of the plurality of subsequent erase verify iterations (Fig. 12: erase verify loop illustrated in steps 1203 through 1206 with read pass applied to dummy word lines. See also col. 24, ln. 4-20; "Step 1204 involves verifying the upper tail of the data memory cells. This can involve evaluating the level of a sense node while concurrently applying an erase-verify voltage to the data word lines and a read pass voltage, Vread, to the dummy word lines and SG transistors", "If the decision step 1205 is false, and the maximum allowable number (#) of erase-verify loops has not yet been reached such that decision step 1206 is false, Verase is incremented at step 1206a and the process continues at step 1203").
Dutta, Tokiwa and Lien combined, as well as Li1 and Li2 are from the same field of endeavor as applicant’s invention directed to the erase verify operation of non-volatile memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Dutta, Tokiwa and Lien's erase verify operation with the additional teachings of Li1’s application of select gate voltages and Li2’s application of dummy word line voltages. Doing so would further result in the reduction of power consumption due to reduced switching current as well as further increased speed during the erase verify operation.
Regarding claims 4, 11, and 17, Dutta, Tokiwa and Lien combined disclose the limitations of claims 1, 8, and 14 respectively.
As applied, Dutta further discloses wherein the plurality of word lines, and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack (Fig. 10C. See also col. 20, ln. 20-22; "Columns of memory cells C0 to C11 are depicted in the multi-layer stack, having layers BG, WL0-WL6, BG, and D0-D8"),
the memory holes extend vertically through the stack (Fig. 10D. See also col. 21, ln. 14-15; "Each block includes rows of columnar, e.g., vertical, memory holes or pillars, represented by circles in FIG. 10D"),
the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes (Fig. 9A: SGD, SGS),
the drain-side select gate transistor of each of the memory holes is connected to one of a plurality of bit lines and the at least one source-side select gate transistor of each of the memory holes is connected to a source line (Fig. 9A where it illustrates the SGD transistor connected to bit lines BL0-BL2 and the SGS transistor connected to the source line through SE0-SE2),
the plurality of word lines includes one or more dummy word lines adjacent at least one of the drain-side select gate transistor and the at least one source-side select gate transistor (Fig. 3 WL0 and WL63. It is noted that the term "dummy word line" appears to be directed to FIG. 3 as well as defined in the instant application in para. 177 as "The plurality of word lines including one or more dummy word lines (e.g., word lines WLO and WL63 of FIG. 3) adjacent at least one of the drain-side select gate transistor and the source-side select gate transistor". It is further noted that Dutta's Fig. 3 is identical to Fig. 3 in the instant application so it would be understood to one of ordinary skill in the art that Dutta's outer word lines could similarly be considered dummy word lines),
the plurality of word lines include a plurality of even numbered word lines and a plurality of odd numbered word lines (Fig. 9B & 9C where it illustrates WL0 and WL28 as an example of a plurality of even numbered word lines and WL31 and WL63 as an example of a plurality of odd numbered word lines),
the at least some of the memory cells of ones of the plurality of strings being erased includes one of the memory cells of the plurality of odd numbered word lines and the memory cells of the plurality of even numbered word lines (Fig. 9B where it illustrates the erase voltage Vev on even numbered word lines and 9C where it illustrates the erase voltage Vev on odd numbered word lines),
the plurality of subsequent erase verify iterations including a plurality of odd subsequent erase verify iterations for the plurality of odd numbered word lines and a plurality of even subsequent erase verify iterations for the plurality of even numbered word lines (Fig. 9B & 9C. See also col. 15, ln. 48-52; "In FIG. 9B, the erase-verify test is performed concurrently for storage elements associated with only the even word lines. In FIG. 9C, the erase-verify test is performed concurrently for storage elements associated with only the odd word lines"),
Dutta, Tokiwa and Lien are silent with respect to specific select gate and dummy word line voltages.
However, Li1 teaches and the control means/controller/method is further configured to:
alternately apply a select gate voltage and a steady state voltage to the drain-side select gate transistor coupled to the memory cells (See Examiner's Markup above and Fig. 6B. See also para. 27; "T1 is when a verification stage begins", "and T3 is when the verification stage ends". It is noted that Li's memory array structure has odd word lines (FIG. 2: WL1, WL3) and even word lines (FIG. 2: WL2, WL4)),
the application of the select gate voltage to the drain-side select gate transistor alternating from the select gate voltage to the steady state voltage for each of the plurality of odd subsequent erase verify iterations and the plurality of even subsequent erase verify iterations (Id and for the same reasons),
the application of the select gate voltage causing the drain-side select gate transistor to be conductive and the application of the select gate voltage to the source-side select gate transistor causing the source-side select gate transistor to be conductive (It is well understood in the art that applying a select gate voltage to a select gate transistor causes the transistor to be conductive);
Li1 is silent with respect to specific word line voltages which may be considered “dummy word lines” although it is noted that the term “dummy word lines” in the instant application apparently applies to nominal data word lines which are merely designated so.
However, Li2 teaches and continuously apply a read pass voltage to the one or more dummy word lines for the entire duration of the plurality of odd subsequent erase verify iterations and the entire duration of the plurality of even subsequent erase verify iterations (Fig. 12: erase verify loop illustrated in steps 1203 through 1206 with read pass applied to dummy word lines. See also col. 24, ln. 4-20; "Step 1204 involves verifying the upper tail of the data memory cells. This can involve evaluating the level of a sense node while concurrently applying an erase-verify voltage to the data word lines and a read pass voltage, Vread, to the dummy word lines and SG transistors", "If the decision step 1205 is false, and the maximum allowable number (#) of erase-verify loops has not yet been reached such that decision step 1206 is false, Verase is incremented at step 1206a and the process continues at step 1203" ).
Dutta, Tokiwa and Lien combined, as well as Li1 and Li2 are from the same field of endeavor as applicant’s invention directed to the erase verify operation of non-volatile memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Dutta, Tokiwa and Lien's erase verify operation with the additional teachings of Li1’s application of select gate voltages and Li2’s application of dummy word line voltages. Doing so would further result in the reduction of power consumption due to reduced switching current as well as further increased speed during the erase verify operation.
Claims 5, 6, 12, 13, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Dutta et al. (US 9343160; “Dutta” – of Record) in view of Tokiwa (US 20210020250 – of Record ), and further in view of Lien et al (US 11335411; "Lien"), and further in view of Li et al. (US 20210335426; “Li1” – of Record), and further in view of Li et al. (US 11335419; “Li2” – of Record), and further in view of Hou et al. (US 20230272638; “Hou” – of Record).
Regarding claims 5, 12, and 18, Dutta, Tokiwa, Lien, Li1 and Li2 combined disclose the limitations of claim 4, 11, and 17 respectively.
As applied, Dutta further discloses wherein the control means/controller/method is further configured to:
apply the erase verify voltage to the plurality of odd numbered word lines and successively determine whether the memory cells of ones of the plurality of strings being erased connected to the plurality of odd numbered word lines have the threshold voltage below the erase verify voltage in the plurality of odd subsequent erase verify iterations (Fig. 9C. See also col. 15, ln. 48-52; " In FIG. 9C, the erase-verify test is performed concurrently for storage elements associated with only the odd word lines"),
and apply the erase verify voltage to the plurality of even numbered word lines and successively determine whether the memory cells of ones of the plurality of strings being erased connected to the plurality of even numbered word lines have the threshold voltage below the erase verify voltage in the plurality of even subsequent erase verify iterations (Fig. 9B. See also col. 15, ln. 48-52; "FIG. 9B, the erase-verify test is performed concurrently for storage elements associated with only the even word lines"),
As applied, Tokiwa further discloses the application of the erase verify voltage to the plurality of odd numbered word lines maintained constantly throughout an entire duration of the plurality of odd subsequent erase verify iterations (Fig. 14 where it illustrates during the erase verify operation of at least strings Str0-Str1, word lines (Wli) are held at the erase verify voltage throughout the duration of the operation. See also Fig. 3 where it illustrates the plurality of strings have a plurality of odd numbered word lines, WL15 and WL9 for example);
the application of the erase verify voltage to the plurality of even numbered word lines maintained constantly throughout an entire duration of the plurality of even subsequent erase verify iterations (Fig. 14 where it illustrates during the erase verify operation of at least strings Str0-Str1, word lines (Wli) are held at the erase verify voltage throughout the duration of the operation. See also Fig. 3 where it illustrates the plurality of strings have a plurality of even numbered word lines, WL10 and WL8 for example),
Dutta, Tokiwa, Lien, Li1, and Li2 are silent with respect to the grouping of even and odd erase verify iterations.
However, Hou teaches each of the plurality of even subsequent erase verify iterations grouped together and carried out sequentially and each of the plurality of odd subsequent erase verify iterations grouped together and carried out sequentially (Fig. 5 where it illustrates even and odd word line erase verify passes in steps 506 & 508. See also para. 62; " Process 500 is a process for erase verify with passed WL inhibit where even and odd wordlines (E/O WL) are verified separately". Further, see para. 63; "In one example, the even word lines are checked, subblock by subblock, followed by the odd word lines, subblock by subblock". It is noted that this method necessarily demonstrates each group (even/odd) is verified together and performed sequentially).
Dutta, Tokiwa, Lien, Li1 and Li2 combined, as well as Hou are from the same field of endeavor as applicant’s invention directed to the erase verify operation of non-volatile memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Dutta, Tokiwa, and Lien's even and odd word line erase verify operation with the teachings of Hou’s sequential grouping of the even and odd word lines. Doing so would reduce the erase disturb effect on physically adjacent memory cells.
Regarding claims 6, 13, and 19, Dutta, Tokiwa, Lien, Li1, Li2 and Hou combined disclose the limitations of claim 5, 12, and 18 respectively.
As applied, Hou further discloses wherein the control means/controller/method is further configured to:
apply a read pass voltage to the plurality of odd numbered word lines while successively determining whether the memory cells of ones of the plurality of strings being erased connected to the plurality of even numbered word lines have the threshold voltage below the erase verify voltage in the plurality of even subsequent erase verify iterations (Fig. 5B: which illustrates even/odd erase verify, and specifically step 580 which sets the odd WL high. See also para. 72; " if all odd wordlines of all subblocks passed erase verify, the logic sets the odd wordline voltage high, at 580. A high voltage is understood to inhibit the wordlines in this example." It is noted that the recited high voltage is necessarily equivalent to a read pass voltage because that set of memory transistors must conduct (be on) regardless of possible threshold voltage state (just as in the read pass case) in order to pass the bit line voltage to the next memory transistor in the string),
the application of the read pass voltage to the plurality of odd numbered word lines maintained constantly throughout the entire duration of the plurality of even subsequent erase verify iterations (Fig. 5B. It is noted that the process flow after step 580 indicates the high voltage applied to the odd WL is maintained through subsequent loop iterations for all even WL of each string/subblock until the erase verify operation is complete in step 576);
and apply the read pass voltage to the plurality of even numbered word lines while successively determining whether the memory cells of ones of the plurality of strings being erased connected to the plurality of odd numbered word lines have the threshold voltage below the erase verify voltage in the plurality of odd subsequent erase verify iterations, (Fig. 5B: which illustrates even/odd erase verify, and specifically step 582 which sets the even WL high. See also para. 72; "Similarly, in one example, if all even wordlines of all subblocks passed erase verify, the logic sets the even wordline voltage high (or to an inhibit voltage), at 582." It is noted that the recited high voltage is necessarily equivalent to a read pass voltage because that set of memory transistors must conduct (be on) regardless of possible threshold voltage state (just as in the read pass case) in order to pass the bit line voltage to the next memory transistor in the string),
the application of the read pass voltage to the plurality of even numbered word lines maintained constantly throughout the entire duration of the plurality of odd subsequent erase verify iterations (Fig. 5B. It is noted that the process flow after step 582 indicates the high voltage applied to the even WL is maintained through subsequent loop iterations for all odd WL of each string/subblock until the erase verify operation is complete in step 576).
Claims 7, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Dutta et al. (US 9343160; “Dutta” – of Record) in view of Tokiwa (US 20210020250 – of Record), and further in view of Lien et al (US 11335411; "Lien") and both in view of and as supported by Hou et al. (US 20230272638; “Hou” – of Record)
Regarding claims 7 and 20, Dutta, Tokiwa and Lien combined disclose the limitations of claims 1 and 14 respectively.
As applied, Dutta further discloses wherein the plurality of word lines include a plurality of even numbered word lines and a plurality of odd numbered word lines (Fig. 9B & 9C where it illustrates WL0 and WL28 as an example of a plurality of even numbered word lines and WL31 and WL63 as an example of a plurality of odd numbered word lines),
the at least some of the memory cells of ones of the plurality of strings being erased includes one of the memory cells of the plurality of odd numbered word lines and the memory cells of the plurality of even numbered word lines (Fig. 9B where it illustrates the erase voltage Vev on even numbered word lines and 9C where it illustrates the erase voltage Vev on odd numbered word lines),
the plurality of subsequent erase verify iterations including a plurality of odd subsequent erase verify iterations for the plurality of odd numbered word lines and a plurality of even subsequent erase verify iterations for the plurality of even numbered word lines (Fig. 9B & 9C. See also col. 15, ln. 48-52; "In FIG. 9B, the erase-verify test is performed concurrently for storage elements associated with only the even word lines. In FIG. 9C, the erase-verify test is performed concurrently for storage elements associated with only the odd word lines"),
and the control means/controller is further configured to:
apply the erase verify voltage to the plurality of even numbered word lines and determine whether the memory cells of each one of the plurality of strings connected to the plurality of even numbered word lines have the threshold voltage below the erase verify voltage in each of the plurality of even subsequent erase verify iterations (Fig. 9B. See also col. 15, ln. 48-52; "FIG. 9B, the erase-verify test is performed concurrently for storage elements associated with only the even word lines");
return to apply the at least one erase pulse to the channel of the memory holes of all of the plurality of strings in response to the memory cells of one of the plurality of strings connected to the plurality of even numbered word lines not having the threshold voltage below the erase verify voltage in one of the plurality of even subsequent erase verify iterations (Fig. 11A & Fig. 11B where it illustrates the process of erase verify and potential successive erase loops (B). It is also observed that step 1076 determines the validity of the erase threshold voltage. As noted above, Dutta discloses even/odd WL erase verify operation);
enter a low current consumption mode in response to the memory cells of a first one of the plurality of strings connected to the plurality of even numbered word lines having the threshold voltage below the erase verify voltage in a first one of the plurality of even subsequent erase verify iterations (Fig. 11B: step 1080. See also col. 17, ln. 39-40; "In step, 880, the system sets up conditions for current saving during the next erase verify that will be performed". Further see col. 18, ln. 19-24; "Another option is to verify memory cells associated with odd word lines separately from those associated with even word lines, as in the examples of FIGS. 9B and 9C. Thus, the examples of FIGS. 9B and 9C can be modified by applying suitable bit line voltages, as shown in FIG. 9E for a current saving mode");
apply the erase verify voltage to the plurality of odd numbered word lines and determine whether the memory cells of each of the plurality of strings connected to the plurality of odd numbered word lines have the threshold voltage below the erase verify voltage in each of the plurality of odd subsequent erase verify iterations in response to the memory cells of a last one of the plurality of strings connected to the plurality of even numbered word lines having the threshold voltage below the erase verify voltage in the last one of the plurality of even subsequent erase verify iterations (Fig. 9C. See also col. 15, ln. 48-52; " In FIG. 9C, the erase-verify test is performed concurrently for storage elements associated with only the odd word lines". Also see col. 18, ln. 42-47; "erase verify can be performed separately for even and odd word lines (see FIGS. 9B, 9C, with modifications to bit line voltages noted above). If erase verify passes at the target erase verify reference level, then the process concludes are step 892".
Examiner notes it appears the above feature may be directed to Figure 18 of the instant application which indicates an ordering of even/odd WLs for the erase verify operation. While Dutta does not recite a specific even/odd WL ordering for the erase verify operation, it is observed that ordering of even/odd WL erase verify would be considered an arbitrary choice between two finite, predictable solutions with a reasonable expectation of success. The choice would be obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention because there is no material difference in functional outcome based on ordering of even and odd WL for the erase verify operation. However, as support for this specific embodiment choice, Hou discloses (Fig. 5B) ordering of the erase verify operation as even WLs (steps 554-560) followed by odd WLs (step 564-570) as in the instant application).
Dutta, Tokiwa and Lien are silent with respect to the specific details regarding determining completion for an even/odd erase verify operation along with recording status of that completion.
However, Hou teaches determine whether the memory cells of each of the plurality of strings connected to the plurality of odd numbered word lines have the threshold voltage below the erase verify voltage while the erase verify voltage is applied to the plurality of odd numbered word lines in each of the plurality of odd subsequent erase verify iterations (Fig. 5C: step 566);
return to apply the at least one erase pulse to the channel of the memory holes of all of the plurality of strings in response to the memory cells of each of the plurality of strings connected to the plurality of odd numbered word lines not having the threshold voltage below the erase verify voltage in one of the plurality of even subsequent erase verify iterations (Fig. 5C: step 586 where it illustrates the process loop going back to step 552 to apply another erase pulse after executing the erase verify operation on the odd WLs in steps 564-570);
and set a status all of the plurality of strings as passing erase verify in response to the memory cells of a last one of the plurality of strings connected to the plurality of odd numbered word lines having the threshold voltage below the erase verify voltage in a last one of the plurality of odd subsequent erase verify iterations (Fig. 5C step 568).
Dutta, Tokiwa and Lien combined, along with Hou are from the same field of endeavor as applicant’s invention directed to the erase verify operation of non-volatile memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Dutta, Tokiwa and Lien’s even and odd word line erase verify operation with the teachings of Hou’s sequential grouping of the even and odd word lines and orderly completion and recording of erase status. Doing so would reduce the erase disturb effect on physically adjacent memory cells and demote defective memory blocks to be disabled which would improve data integrity.
Response to Arguments
Applicant's arguments with respect to independent claims 1, 8 and 14 have been fully considered but they are not persuasive because, while the applicant's contention that the amendments which narrowed the claim scope are not disclosed by the previously applied reference, the new features which required further consideration and search resulting in new references, remains unpatentable under a new ground of rejection.
Accordingly, all dependent claims also remain rejected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825