DETAILED ACTION
This Office Action is in response to the election filed on 06 March 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 4 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06 March 2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 9,196,361 B2; hereinafter Lee), in view of Linn et al. (US 2021/0162738 A1; hereinafter Linn).
In regards to claim 1, Lee teaches a structure comprising:
a first switching memory element (110) (col. 2/lns. 53-67; col. 3/lns. 1-4); and
an access device (120) including a first terminal (e.g. well terminal) coupled to the first switching memory element, a second terminal (e.g. connected to gate signal line), and a layer (e.g. (GL)) between the first terminal and the second terminal (col. 2/lns. 53-67; col. 3/lns. 1-4).
Lee appears to be silent as to, but does not preclude, the limitations of a two-terminal; and a first semiconductor layer wherein, the first semiconductor layer is electrically floating in the structure. Linn teaches the limitations of a two-terminal ([0042-0043]: latched up floating gate transistor); and a first semiconductor layer wherein, the first semiconductor layer is electrically floating in the structure ([0042-0043]: e.g. floating gate transistor). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Lee with the aforementioned limitations taught by Linn to have a memory with a logic circuit, e.g. for read/write (Linn [0042-0043]).
In regards to claim 2, the combination of Lee and Linn teaches the limitations discussed above in addressing claim 1. Lee further teaches the limitations wherein the first switching memory element (110) is a resistive random access memory element (col. 2/lns. 53-67; col. 3/lns. 1-4) that includes a first electrode (e.g. electrode connected to the signal line), a second electrode (e.g. electrode connected to a terminal of the transistor), and a switching layer (e.g. as inferred by the element being a resistive memory element) between the first electrode and the second electrode (col. 2/lns. 53-67; col. 3/lns. 1-4).
In regards to claim 20, Lee teaches a method comprising:
forming an access device (120) including a first terminal (e.g. well terminal), a second terminal (e.g. connected to gate signal line);
a layer (e.g. (GL)) between the first terminal and the second terminal (col. 2/lns. 53-67; col. 3/lns. 1-4); and
forming a switching memory element coupled to the first terminal (110) (col. 2/lns. 53-67; col. 3/lns. 1-4).
Lee appears to be silent as to, but does not preclude, the limitations of forming a two-terminal; and a semiconductor layer, wherein the semiconductor layer is electrically floating in the structure. Linn teaches the limitations of forming a two-terminal ([0042-0043]: latched up floating gate transistor); and a semiconductor layer, wherein the semiconductor layer is electrically floating in the structure ([0042-0043]: e.g. floating gate transistor). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Lee with the aforementioned limitations taught by Linn to have a memory with a logic circuit, e.g. for read/write (Linn [0042-0043]).
Claim(s) 3 and 6-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lee and Linn as applied to claim 1 above, in view of Hideki et al. (US 2004/0165422 A1; hereinafter Hideki).
In regards to claim 3, the combination of Lee and Linn teaches the limitations discussed above in addressing claim 1. The combination of Lee and Linn appears to be silent as to, but does not preclude, the limitations wherein the first switching memory element is a phase change memory element that includes a first electrode, a second electrode, and a layer of phase change material between the first electrode and the second electrode. Hideki teaches, e.g. in fig. 7, the limitations wherein the first switching memory element (124) is a phase change memory element [0047] that includes a first electrode (119), a second electrode (123), and a layer of phase change material (121) between the first electrode and the second electrode [0047]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Lee and Linn with the aforementioned limitations taught by Hideki to have a layout of a memory element that affects current density and how efficiently a phase-change element operates (Hideki [0047]).
In regards to claim 6, the combination of Lee and Linn teaches the limitations discussed above in addressing claim 1. Lee further teaches the limitations wherein the first terminal (e.g. well terminal) comprises a well in the semiconductor substrate and a first doped region in the well (col. 2/lns. 53-67; col. 3/lns. 1-4), and the first switching memory element is coupled to the first doped region (e.g. by the access device) (col. 2/lns. 53-67; col. 3/lns. 1-4).
The combination of Lee and Linn appears to be silent as to, but does not preclude, the limitations of a semiconductor substrate. Hideki teaches, e.g. in fig. 7, the limitations of a semiconductor substrate (100) [0052]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Lee and Linn with the aforementioned limitations taught by Hideki to have a layout of a memory element that affects current density and how efficiently a phase-change element operates (Hideki [0047]).
In regards to claim 7, the combination of Lee, Linn, and Hideki teaches the limitations discussed above in addressing claim 6. Lee further teaches the limitations wherein the first semiconductor layer is disposed on a portion of the well (e.g. well terminal), the first terminal comprises a second doped region disposed in the portion of the well (col. 2/lns. 53-67; col. 3/lns. 1-4).
Hideki further teaches the limitations of a shallow trench isolation region in the semiconductor substrate, the shallow trench isolation region disposed laterally between the first doped region and the second doped region [0053]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Lee and Linn with the aforementioned limitations taught by Hideki to have a layout of a memory element that affects current density and how efficiently a phase-change element operates (Hideki [0047]).
In regards to claim 8, the combination of Lee and Linn teaches the limitations discussed above in addressing claim 1. Linn further teaches the limitations of a first semiconductor layer ([0042-0043]: e.g. floating gate transistor); and wherein first terminal is a second semiconductor layer disposed on the first semiconductor layer, and the first switching memory element is coupled to the second semiconductor layer ([0042-0043]: e.g. floating gate transistor). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Lee with the aforementioned limitations taught by Linn to have a memory with a logic circuit, e.g. for read/write (Linn [0042-0043]).
The combination of Lee and Linn appears to be silent as to, but does not preclude, the limitations of a semiconductor substrate, wherein the first layer is disposed on a portion of the semiconductor substrate. Hideki teaches the limitations of a semiconductor substrate (100) [0052], wherein the first layer (e.g. (105)) [0052] is disposed on a portion of the semiconductor substrate (100) [0052]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Lee and Linn with the aforementioned limitations taught by Hideki to have a layout of a memory element that affects current density and how efficiently a phase-change element operates (Hideki [0047]).
In regards to claim 9, the combination of Lee, Linn, and Hideki teaches the limitations discussed above in addressing claim 8. Hideki further teaches the limitations further comprising: a second switching memory element coupled to the second semiconductor layer (fig. 7: multiple transistors connected to multiple memory elements). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Lee and Linn with the aforementioned limitations taught by Hideki to have a layout of a memory element that affects current density and how efficiently a phase-change element operates (Hideki [0047]).
In regards to claim 10, the combination of Lee, Linn, and Hideki teaches the limitations discussed above in addressing claim 9. Hideki further teaches the limitations further comprising: a back-end-of-line stack disposed on the semiconductor substrate (e.g. elements in layers (115) and up), wherein the first switching memory element and the second switching memory element are disposed in the back-end-of-line stack (e.g. stacks (124)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Lee and Linn with the aforementioned limitations taught by Hideki to have a layout of a memory element that affects current density and how efficiently a phase-change element operates (Hideki [0047]).
In regards to claim 11, the combination of Lee, Linn, and Hideki teaches the limitations discussed above in addressing claim 8. Hideki further teaches the limitations wherein the semiconductor substrate (100) has a top surface (e.g. upper surface of (100)), the first semiconductor layer (e.g. the gate stack including (105)) directly contacts the top surface of the semiconductor substrate (fig. 9H: e.g. gate stack including (105) directly contacts the upper surface of (100)), and further comprising:
a first dielectric spacer (fig. 9H: e.g. one of the gate stack sidewall spacers) in direct contact with the top surface of the semiconductor substrate;
and a second dielectric spacer (fig. 9H: e.g. another of the gate stack sidewall spacers) in direct contact with the top surface of the semiconductor substrate,
wherein the first semiconductor layer and the second semiconductor layer are disposed between the first dielectric spacer and the second dielectric spacer (fig. 9H).
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Lee and Linn with the aforementioned limitations taught by Hideki to have a layout of a memory element that affects current density and how efficiently a phase-change element operates (Hideki [0047]).
In regards to claim 12, the combination of Lee, Linn, and Hideki teaches the limitations discussed above in addressing claim 11. Hideki further teaches the limitations wherein the first dielectric spacer (fig. 9H: e.g. one of the gate stack sidewall spacers) is separated from the second dielectric spacer (fig. 9H: e.g. another of the gate stack sidewall spacers) by a spacing (fig. 9H: e.g. by a gate stack), and the first semiconductor layer and the second semiconductor layer have respective widths that are each equal to the spacing (fig. 9H: e.g. the first and second spacers directly contact the respective side walls of a gate stack). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Lee and Linn with the aforementioned limitations taught by Hideki to have a layout of a memory element that affects current density and how efficiently a phase-change element operates (Hideki [0047]).
In regards to claim 13, the combination of Lee, Linn, and Hideki teaches the limitations discussed above in addressing claim 11. Hideki further teaches the limitations wherein the first semiconductor layer and the second semiconductor layer each terminate at the first dielectric spacer, and the first semiconductor layer and the second semiconductor layer each terminate at the second dielectric spacer (fig. 9H: e.g. the first and second spacers directly contact the respective side walls of a gate stack).. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Lee and Linn with the aforementioned limitations taught by Hideki to have a layout of a memory element that affects current density and how efficiently a phase-change element operates (Hideki [0047]).
In regards to claim 14, the combination of Lee and Linn teaches the limitations discussed above in addressing claim 1. Lee further teaches the limitations wherein the first semiconductor layer is disposed on a portion of the semiconductor substrate (e.g. well terminal) (col. 2/lns. 53-67; col. 3/lns. 1-4).
The combination of Lee and Linn appears to be silent as to, but does not preclude, the limitations of a semiconductor substrate. Hideki teaches the limitations of a semiconductor substrate (100) [0052]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Lee and Linn with the aforementioned limitations taught by Hideki to have a layout of a memory element that affects current density and how efficiently a phase-change element operates (Hideki [0047]).
In regards to claim 15, the combination of Lee, Linn, and Hideki teaches the limitations discussed above in addressing claim 14. Hideki further teaches the limitations wherein the semiconductor substrate (100) has a top surface (e.g. upper surface of (100)), the first semiconductor layer (e.g. the gate stack including (105)) directly contacts the top surface of the semiconductor substrate (fig. 9H: e.g. gate stack including (105) directly contacts the upper surface of (100)), and further comprising:
a first dielectric spacer (fig. 9H: e.g. one of the gate stack sidewall spacers) in direct contact with the top surface of the semiconductor substrate;
and a second dielectric spacer (fig. 9H: e.g. another of the gate stack sidewall spacers) in direct contact with the top surface of the semiconductor substrate,
wherein the first semiconductor layer and the second semiconductor layer are disposed between the first dielectric spacer and the second dielectric spacer (fig. 9H).
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Lee and Linn with the aforementioned limitations taught by Hideki to have a layout of a memory element that affects current density and how efficiently a phase-change element operates (Hideki [0047]).
In regards to claim 16, the combination of Lee, Linn, and Hideki teaches the limitations discussed above in addressing claim 15. Linn further teaches the limitations wherein the second terminal is a second semiconductor layer is disposed on the first semiconductor layer, and the second semiconductor layer is disposed between the first dielectric spacer and the second dielectric spacer ([0042-0043]: e.g. floating gate transistor). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Lee with the aforementioned limitations taught by Linn to have a memory with a logic circuit, e.g. for read/write (Linn [0042-0043]).
In regards to claim 17, the combination of Lee, Linn, and Hideki teaches the limitations discussed above in addressing claim 16. Hideki further teaches the limitations wherein the first semiconductor layer and the second semiconductor layer are coextensive with the spacer (fig. 9H: e.g. the first and second spacers directly contact the respective side walls of a gate stack). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Lee and Linn with the aforementioned limitations taught by Hideki to have a layout of a memory element that affects current density and how efficiently a phase-change element operates (Hideki [0047]).
In regards to claim 18, the combination of Lee, Linn, and Hideki teaches the limitations discussed above in addressing claim 16. Hideki further teaches the limitations wherein the first semiconductor layer and the second semiconductor layer terminate at the spacer (fig. 9H: e.g. the first and second spacers directly contact the respective side walls of a gate stack). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Lee and Linn with the aforementioned limitations taught by Hideki to have a layout of a memory element that affects current density and how efficiently a phase-change element operates (Hideki [0047]).
In regards to claim 19, the combination of Lee, Linn, and Hideki teaches the limitations discussed above in addressing claim 14. Hideki further teaches the limitations further comprising: a back-end-of-line stack on the semiconductor substrate (e.g. elements in layers (115) and up), wherein the first switching memory element is disposed in the back-end-of-line stack above the two-terminal access device (e.g. stacks (124)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Lee and Linn with the aforementioned limitations taught by Hideki to have a layout of a memory element that affects current density and how efficiently a phase-change element operates (Hideki [0047]).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lee and Linn as applied to claim 1 above, and further in view of Lim et al. (US 2011/0278657 A1; hereinafter Lim).
In regards to claim 5, the combination of Lee and Linn teaches the limitations discussed above in addressing claim 1. The combination of Lee and Linn appears to be silent as to, but does not preclude, the limitations wherein the first semiconductor layer comprises silicon-germanium. Lim teaches the limitations wherein the first semiconductor layer comprises silicon-germanium [0044-0045]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Lee and Linn with the aforementioned limitations taught by Lim to select materials based on a floating layer function (Lim [0044-0045]).
Conclusion
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812
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