DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/15/2023 was filed and is in
compliance with provision of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
On page 1, line 18, the “diode chip” is referenced using the number 71 (referring to fig. 7). However, on page 1, lines 21 and 24, and on page 2, lines 1 and 4, the “diode chip” is referenced using the number 72.
This is informal and unclear since on page 1, line 19, the “n-type doped layer” is referenced using the number 72. The same reference number is used for different elements of the invention. It is suggested to use the correct reference number for corresponding elements.
In the specification page 2, line 13, 18, 20… the term “epitaxy layer” is used to refer to the layer 102 on the substrate. The word “epitaxy” means a process of growing a crystalline layer on a substrate, while the word “epitaxial” is a layer produced by the process epitaxy. The term “epitaxy layer” is indefinite because in the context of claim 1 it is believed by the examiner applicant is referring to the particular layer but not the process itself. It is suggested where applicant recites epitaxy layer applicant should change it to epitaxial layer. Appropriate correction is required.
Claim Objections Regarding claim 1, lines 1, 7, 9 and line 17 the term “epitaxy layer” is used to refer the layer on the substrate. The word “epitaxy” means a process of growing a crystalline layer on a substrate, while the word “epitaxial” is a layer produced by the process epitaxy. The term “epitaxy layer” is indefinite because in the context of claim 1 it is believed by the examiner applicant is referring to the particular layer but not the process itself. It is suggested where applicant recites epitaxy layer applicant should change it to epitaxial layer. Depending claims 2-6 are also objected to as they depend on claim 1.
Regarding claim 1, line 7 and line 17 recite word “diffusing” which is informal. The examiner suggests changing the word to “extending”.
Dependent claims 2-6 are also objected to as they depend on claim 1.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, line 18, recites “p-type doped regions P+”, however, there is no antecedent basis for “p-type doped regions P+” since the term is not mentioned earlier in claim 1. It is suggested to add “p-type doped regions P+” in claim 1 to overcome this issue. Appropriate correction is required.
Dependent claims 2-6 are also rejected as they depend on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claims 1-6, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Urienza (US 8, 368,167 B1) in view of Arima et al. (US 12396188 B2).
Regarding claim 1, Urienza teaches a Schottky diode comprising:
a substrate (201; Urienza fig.2A) having an epitaxy layer (203; Urienza fig.2A), wherein the epitaxy layer is partitioned into a cathode region (N+ region; Urienza fig.2A) and an anode region (P+ region; Urienza fig.2A) beside the cathode region;
a cathode structure formed in the cathode region of the substrate and
comprising:
a heavily doped n-type region (207; Urienza fig.2A) diffusing from a surface of the epitaxy layer into the substrate;
a lightly doped n-type region (N -; Urienza annotated fig. 2A) formed in the epitaxy layer and around the highly doped n-type region; and
a cathode contact (206; Urienza fig.3B) formed on and contacting the heavily doped n-type region, wherein the cathode contact is composed of multiple stacked metal material layers (317; Urienza fig.3B); and
an anode structure, electrically insulated from the cathode structure, formed in the anode region of the substrate and comprising:
a plurality of p-type doped regions (208; Urienza fig.2A), each p-type doped region diffusing from the surface of the epitaxy layer into the substrate, wherein each adjacent two of the p-type doped regions P+ are separated by an interval (width; Urienza fig.2A); and
an anode contact (205; Urienza fig.2A) formed on and contacting the plurality of the p-type doped regions, wherein the anode contact protrudes from the substrate and is composed of multiple stacked metal material layers (512; Urienza fig.5B).
However, Urienza does not teach a backside metal film formed on a back surface of the substrate;
Arima et al. teaches a backside metal film (50; fig. 2) formed on a back surface of the substrate (20; fig. 2);
Urienza and Arima et al. are analogous art to the claimed invention because they both are directed to semiconductor devices with Schottky diode and one of the ordinary skill in the art would have had a reasonable expectation of success to modify Urienza in view of Arima et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing
date of the claimed invention to modify Urienza to have added a backside metal film formed on a back surface of the substrate as a part of the cathode as taught by Arima (col 10, line 53) to increase the conductivity of the substrate, thus reducing the resistivity of the substrate, which plays significant role to reduce the forward voltage of the Schottky diode.
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Urienza Fig.2A
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Urienza Fig.3B
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Urienza Fig.5B
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Arima et al. Fig.2
Regarding claim 2, Urienza and Arima et al. teach the Schottky diode as claimed in claim 1. Urienza further teaches wherein a surface insulative layer (204; Urienza fig.2A) is formed on the substrate (201; Urienza fig.2A) to electrically insulate the cathode structure from the anode structure and is flush with periphery sidewalls (at least the vertical boundary walls of substrate; Urienza fig.2A) of the substrate.
Regarding claim 3, Urienza and Arima et al. teach the Schottky diode as claimed in claim 2. Urienza further teaches wherein the surface insulative layer (204; Urienza fig.2A) is composed of SiO2, Si3N4 (col. 3, line 28).
However, Urienza does not explicitly teach wherein the surface insulative layer comprises a surface dielectric layer composed of polyimide and a dielectric layer composed of tetraethoxysilane.
It would have been obvious to one having ordinary skill in the art before the effective
filing date of the claimed invention to modify the surface insulative layer composed of SiO2, Si3N4 in Urienza by having it be composed of a surface dielectric layer composed of polyimide and a dielectric layer composed of tetraethoxysilane, since polyimide and tetraethoxysilane have similar dielectric, thermal and mechanical properties to that of SiO2 and Si3N4. This is a general substitution of dielectric layers, in the absence of any criticality or unexpected results disclosed by Applicant for the materials of the surface insulative layer. Materials which are generally substituted for the same purpose in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characterization during fabrication. Additionally, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 4, Urienza and Arima et al. teach the Schottky diode as claimed in claim 1. Urienza further teaches wherein an outermost one of the pluralities of the p-type doped regions (left-most or right-most P+ region; Urienza annotated fig.2A) is spaced apart (gap between P+ and N-; Urienza annotated fig.2A) from the lightly doped n-type region (segmented or interrupted portions of the N – region; Urienza annotated fig.2A) by a lateral distance.
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Urienza Annotated fig. 2A
Regarding claim 5, Urienza and Arima et al. teach the Schottky diode as claimed in claim 1. Urienza further teaches wherein,
the substrate is a silicon substrate (201; Urienza fig.2A);
the cathode contact (206; Urienza fig.3B) comprises a silicide metal film (PtSi, TiSi2, NiSi), a cathode conductive layer (Pt, Ti, Al, Ni or any other suitable material col 3, line 27) and a contact metal layer (Pt, Ti, Al, Ni or any other suitable material col 3, line 27);
the anode contact (205; Urienza fig.3B) comprises a silicide metal film (PtSi, TiSi2, NiSi), an anode conductive layer (Pt, Ti, Al, Ni or any other suitable material col 3, line 27) and a contact metal layer (Pt, Ti, Al, Ni or any other suitable material col 3, line 27);
Urienza does not explicitly teach both the cathode contact and the anode contact comprise a silicide metal film, a conductive layer and a contact metal layer (tri-layer contact of silicide/metal/metal). Urienza also does not explicitly teach the cathode conductive layer and anode conductive layer include an aluminum material; and the contact metal layers of the cathode contact and anode contact include a copper material.
However, materials which are generally substituted for the same purpose in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characterization during fabrication.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Urienza by having the cathode and the anode contacts comprise a silicide metal film, a conductive layer and a contact metal layer, (at least a tri-layer contact), since Urienza teaches the cathode and anode contacts can comprise multiple silicide layers such as Ptsi, TiSi2, and NiSi with multiple metal layers such as Pt, Ti, Al, and Ni with the motivation that multiple metal and silicide layered contacts are conventional and can be tailored by routine experimentation to produce the desired and optimized conductivity and resistance in the device contact, especially since Applicant has not expressed or disclosed any criticality or unexpected results for these metals or their layered arrangement.
Additionally, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Urienza by having the cathode conductive layer and the anode conductive layer include an aluminum layer; and the contact metal layers of the cathode contact and the anode contact include a copper material with the motivation that aluminum and copper have similar electrical conductivity, low resistivity and thermal stability to Pt, Ti and Ni. These metals also are conventional and can be added into a multilayered contact and tailored by routine experimentation to produce the desired and optimized conductivity and resistance in the device contact, especially since Applicant has not expressed or disclosed any criticality or unexpected results for these metals or their layered arrangement.
Regarding claim 6, Urienza and Arima et al. teach the Schottky diode as claimed in claim 1. Urienza further teaches wherein the substrate (201; Urienza fig.2A) has uncovered periphery sidewalls (at least the vertical boundary walls of substrate; Urienza fig.2A) being directly exposed;
However, Urienza and Arima et al. do not teach a backside protective cover is formed on the backside metal film.
Arima et al. teaches a backside metal film is formed on a back surface of the substrate. The metal film is made of a “multilayer structure of different metal films, such as Ti/Au or Ti/Al” (Arima et al. col 4, line 18).
Urienza and Arima et al. are analogous art to the claimed invention because they both are directed to semiconductor devices with Schottky diode and one of the ordinary skills in the art would have had a reasonable expectation of success to modify Urienza in view of Arima et al. because they are from the same field of endeavor.
It would have been obvious to one having ordinary skill in the art before the effective
filing date of the claimed invention to modify Urienza by substituting the multiple layer metal film taught by Arima made of for example Ti/Au or Ti/Al with two layers as a backside protective cover formed on the backside metal film, since the backside protective cover can protect the backside metal film.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RUDRA B CHAUDHARY whose telephone number is (571)272-9292. The examiner can normally be reached Monday-Friday 7:30 a.m. - 5:00 p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.B.C./Examiner, Art Unit 2811
/LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811
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