Technology area: Semiconductors, Circuits & Optics
5 pending office actions • 4 art units • 5 examiners • 0 of 5 (0%) have an AI response strategy ready • 9 patents granted in the last 365 days
Panjit International Inc. currently manages 6 pending office actions within the Semiconductors, Circuits & Optics technology area. These matters are distributed across 4 distinct art units, which indicates that the company's prosecution activity involves several different technical classifications within the patent office.
The workload is spread among 6 distinct examiners. This distribution means that every pending office action is currently assigned to a different individual. This ratio between pending actions and examiners suggests that the applicant must manage interactions with a diverse group of patent office personnel simultaneously.
EUGENE LEE is identified as the busiest examiner for this portfolio. This examiner is currently responsible for 1 pending office action. While the portfolio involves distinct examiners in total, the presence of 4 distinct art units shows that the legal challenges are not confined to a single specialized group.
Based on the USPTO statutory response window for each pending office action. 2 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 2 (40%) |
| Multi-statute (no §101) | 3 (60%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| LEE, EUGENE | 1 | 81.9% | +5.8% |
| SMITH, SAMUEL JONATHAN | 1 | 83.7% | +5.7% |
| NGUYEN, SOPHIA T | 1 | 44.7% | +14.4% |
| SANDVIK, BENJAMIN P | 1 | 76.9% | +6.2% |
| GURLEY, LYNNE ANN | 1 | 2.7% | +16.7% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 1 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18437128 | SEMICONDUCTOR PACKAGE STRUCTURE AND BYPRODUCT OF SEMICONDUCTOR COMPONENT | SMITH, SAMUEL JONATHAN | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18527703 | FLAT SEMICONDUCTOR PACKAGE WITH COPLANAR LEADS | SANDVIK, BENJAMIN P | 8d overdue |
| 18764577 | ULTRA-THIN PACKAGED COMPONENT | LEE, EUGENE | — |
| 18509657 | SCHOTTKY DIODE WITH LOW REVERSE CURRENT AND HIGH HEAT DISSIPATION EFFECT | GURLEY, LYNNE ANN | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18399678 | METHOD OF MANUFACTURING PRE-MOLDED LEAD FRAME FOR PACKAGING | NGUYEN, SOPHIA T | 2d overdue |
| 18509657 | SCHOTTKY DIODE WITH LOW REVERSE CURRENT AND HIGH HEAT DISSIPATION EFFECT | GURLEY, LYNNE ANN | — |
| Art Unit | Apps |
|---|---|
| 2817 | 1 |
| 2893 | 1 |
| 2812 | 1 |
| 2811 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18764577 | ULTRA-THIN PACKAGED COMPONENT | LEE, EUGENE | — | §103§112 | Non-Final OA | — | Pending | Jul 05, 2024 |
| 18437128 | SEMICONDUCTOR PACKAGE STRUCTURE AND BYPRODUCT OF SEMICONDUCTOR COMPONENT | SMITH, SAMUEL JONATHAN | 2817 | §103 | Non-Final OA | — | Pending | Feb 08, 2024 |
| 18399678 | METHOD OF MANUFACTURING PRE-MOLDED LEAD FRAME FOR PACKAGING | NGUYEN, SOPHIA T | 2893 | §103 | Non-Final OA | 2d overdue | Pending | Dec 28, 2023 |
| 18527703 | FLAT SEMICONDUCTOR PACKAGE WITH COPLANAR LEADS | SANDVIK, BENJAMIN P | 2812 | §102§103§112 | Final Rejection | 8d overdue | Pending | Dec 04, 2023 |
| 18509657 | SCHOTTKY DIODE WITH LOW REVERSE CURRENT AND HIGH HEAT DISSIPATION EFFECT | GURLEY, LYNNE ANN | 2811 | §103§112 | Non-Final OA | — | Pending | Nov 15, 2023 |
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