DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in the COUNTRY OF KOREA on 02/21/2023.
Election/Restrictions
Applicant's election without traverse of “Species B (Claims 1-7 and 9-20)” in the reply filed on 03/19/2026, is acknowledged. After Examiner’s review of “Species B” election, claims 7,15 and 20 are also withdrawn from further consideration because these claims are drawn to nonelected species.
Claim 7 reads on Species C and D, wherein “the lower chip pads and the upper chip pads are respectively in direct contact with each other between adjacent first semiconductor chips of the first semiconductor chips” (no chip terminals present).
Claim 15 reads on Species C and D, wherein “a lower chip pads and upper chip pads are in direct contact with each other between adjacent semiconductor chips of the semiconductor chips” (no chip terminals present).
Claim 20 reads on Species A, wherein the second semiconductor chip does not comprise vertically penetrating vias.
Claims 7-8,15 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “220” has been used to designate both “second vias” and “third vias”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6,9-14 and 16-19 are rejected under 35 U.S.C. 103 as being obvious over US 2017/0243856 A1; Park et al.; 08/2017; (“856”) in view of US 9,818,625 B2; Li et al.; 11/2017; (“625”).
Regarding Claim 1. 856 teaches in Fig. 5 about a semiconductor package, comprising:
a semiconductor substrate (item 100) comprising a plurality of first vias (item 100 comprises items 120);
a chip stack (item 200) on the semiconductor substrate (item 200 is on item 100), the chip stack comprising first semiconductor chips on the semiconductor substrate (items 210,220a and 220b are on item 100), and a second semiconductor chip (item 230) on an uppermost first semiconductor chip of the first semiconductor chips (item 230 is on an uppermost first semiconductor chip item 220b); and
a mold layer (item 500) on the semiconductor substrate and a portion of the chip stack (item 500 is on item 100 and a portion of item 200),
wherein a third thickness of the second semiconductor chip is less than or equal to the second thickness of each of the first semiconductor chips (“the upper semiconductor chip 230 may have a thickness substantially the same as those of the lower semiconductor chip 210 and the first and second middle semiconductor chips 220a and 220b”, [0041], Ln. 1-4),
wherein the semiconductor substrate further comprises lower substrate pads (items 145) on a bottom surface of the semiconductor substrate (items 145 are on a bottom surface of item 100),
wherein each of the first semiconductor chips comprises lower chip pads (items 217,227a and 227b) on a bottom surface of each of the first semiconductor chips (items 217,227a and 227b are part of each bottom surface of each of the first semiconductor chips).
856 does not teach about a semiconductor package, comprising:
a mold layer exposing a top surface of the chip stack,
wherein a first thickness of the semiconductor substrate is greater than a second thickness of each of the first semiconductor chips, and
wherein a first width of each of the lower substrate pads is greater than a second width of each of the lower chip pads.
625 teaches in Fig. 6 about a semiconductor package, comprising:
a mold layer (item 518) exposing a top surface of the chip stack (item 518 exposes a top surface of item 103),
wherein a first thickness of the semiconductor substrate is greater than a second thickness of each of the first semiconductor chips (thickness of substrate item 106 is greater than the thickness of any of the semiconductor chips from item 103).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the mold layer exposing a top surface of the chip stack and the thicker substrate when compared to the thickness of the chips within the chip stack of 625 to provide the chip stack with an exposed top surface for thermal conductivity through an opening of the mold layer and for greater substrate rigidity in 856 as taught by 625 in Fig. 5.
856 in view of 625 does not teach about a semiconductor package, comprising:
wherein a first width of each of the lower substrate pads is greater than a second width of each of the lower chip pads.
It would have been an obvious matter of design choice to experiment using greater width lower substrate pads compared to the width of the lower chip pads, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding Claim 2. 856 teaches in Fig. 5 about a semiconductor package, wherein the third thickness of the second semiconductor chip is greater than the second thickness of each of the first semiconductor chips.
856 does not teach about a semiconductor package, wherein the third thickness of the second semiconductor chip is equal to the second thickness of each of the first semiconductor chips.
It would have been an obvious matter of design choice to experiment using different relative thicknesses of the first and second semiconductor chips, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding Claim 3. 856 teaches in Fig. 5 about a semiconductor package, wherein the second semiconductor chip comprises a chip, a type of the chip being same as a type of each of the first semiconductor chips (“the plurality of semiconductor chips 210, 220a, 220b and 230 may be memory chips”, [0019], Ln. 6-7).
Regarding Claim 4. 625 teaches in Fig. 5 about a semiconductor package, wherein the second semiconductor chip (top semiconductor chip of the chip stack item 103) comprises second vias vertically penetrating the second semiconductor chip (via items 112 are vertically penetrating the top semiconductor chip of the chip stack item 103).
Regarding Claim 5. 856 teaches in Fig. 5 about a semiconductor package, wherein the second semiconductor chip comprises a chip, a type of the chip being different from a type of each of the first semiconductor chips (“the plurality of semiconductor chips 210, 220a, 220b and 230 may be of the same type”, [0019], Ln. 4-5),
wherein each of the first semiconductor chips comprises third vias vertically penetrating each of the first semiconductor chips (chip items 210,220a and 220b are vertically penetrated by via items 215,225a and 225b respectively).
Regarding Claim 6. 856 teaches in Fig. 5 about a semiconductor package, wherein the first thickness of the semiconductor substrate, the second thickness of each of the first semiconductor chips and the third thickness of the second semiconductor chip are not disclosed.
856 does not teach about a semiconductor package, wherein the first thickness of the semiconductor substrate ranges from 30 µm to 60 µm, and
wherein the second thickness of each of the first semiconductor chips and the third thickness of the second semiconductor chip range from 20 µm to 40 µm.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to experiment with different thickness ranges for the semiconductor substrate and the first and second semiconductor chips, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding Claim 9. 856 teaches in Fig. 5 about a semiconductor package, wherein a width of the semiconductor substrate is greater than a width of the chip stack in a horizontal direction (width of item 100 is greater that the width of item 200 in a horizontal direction).
Regarding Claim 10. 856 teaches in Fig. 5 about a semiconductor package, wherein the semiconductor substrate is a silicon wafer (“substrate 100 may be a … silicon wafer”, [0018], Ln. 3-4), and
wherein each of the first semiconductor chips is a memory chip (“the plurality of semiconductor chips 210, 220a, 220b … may be memory chips”, [0019], Ln. 6-7).
Regarding Claim 11. 856 teaches in Fig. 5 about a semiconductor package, wherein a number of the first semiconductor chips included in the chip stack is 3 (items 210,220a and 220b).
856 does not teach about a semiconductor package, wherein a number of the first semiconductor chips included in the chip stack ranges from 3 to 15.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to experiment with a different number of first semiconductor chips within a chip stack, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding Claim 12. 856 teaches in Fig. 5 about a semiconductor package, comprising:
a semiconductor substrate (item 100) comprising a plurality of first vias (item 100 comprises items 120);
semiconductor chips on the semiconductor substrate (semiconductor chips of item 200 are on item 100); and
a mold layer (item 500) on the semiconductor substrate and the semiconductor chips (item 500 is on item 100 and a portion of the semiconductor chips of item 200),
wherein a first width of the semiconductor substrate is greater than a second width of the chip stack in a horizontal direction (width of item 100 is greater that the width of item 200 in a horizontal direction),
856 does not teach about a semiconductor package, comprising:
each of the semiconductor chips comprising second vias vertically penetrating the semiconductor chips; and
a mold layer exposing a top surface of an uppermost semiconductor chip of the semiconductor chips,
wherein the semiconductor substrate has a first thickness in a vertical direction,
wherein the semiconductor chips have second thicknesses, which are equal to each other, in the vertical direction, and
wherein the first thickness is greater than the second thicknesses.
625 teaches in Fig. 6 about a semiconductor package, comprising:
each of the semiconductor chips comprising second vias vertically penetrating the semiconductor chips (all semiconductor chips within item 103 comprise vias vertically penetrating the semiconductor chips); and
a mold layer (item 518) exposing a top surface of an uppermost semiconductor chip of the semiconductor chips (item 518 exposes a top surface of item 103),
wherein the semiconductor substrate has a first thickness in a vertical direction (thickness of item 106),
wherein the semiconductor chips have second thicknesses (thickness of semiconductor chips within item 103), which are equal to each other, in the vertical direction (thicknesses of semiconductor chips within item 103 are equal to each other in a vertical direction), and
wherein the first thickness is greater than the second thicknesses (thickness of item 106 is greater than the thicknesses of semiconductor chips within item 103).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the mold layer exposing a top surface of the chip stack and the thicker substrate when compared to the thickness of the chips within the chip stack of 625 to provide the chip stack with an exposed top surface for thermal conductivity through an opening of the mold layer and for greater substrate rigidity in 856 as taught by 625 in Fig. 5.
Regarding Claim 13. 856 teaches in Fig. 5 about a semiconductor package, wherein the first thickness of the semiconductor substrate and the second thickness of each of the semiconductor chips are not disclosed.
856 does not teach about a semiconductor package, wherein the first thickness of the semiconductor substrate ranges from 30 μm to 60 μm, and
wherein the second thicknesses of each of the semiconductor chips ranges from 20 μm to 40 μm.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to experiment with different thickness ranges for the semiconductor substrate and the semiconductor chips, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding Claim 14. 856 teaches in Fig. 5 about a semiconductor package, wherein the semiconductor substrate is a silicon wafer (“substrate 100 may be a … silicon wafer”, [0018], Ln. 3-4), and
wherein each of the semiconductor chips is a memory chip (“the plurality of semiconductor chips 210, 220a, 220b and 230 may be memory chips”, [0019], Ln. 6-7).
Regarding Claim 16. 856 teaches in Fig. 5 about a semiconductor package, wherein chip terminals (items 310 and 330) are between a semiconductor chip of the semiconductor chips and the semiconductor substrate or adjacent semiconductor chips of the semiconductor chips (items 310 and 330 are between semiconductor chips and between the lowest semiconductor chip and the substrate),
wherein the semiconductor substrate further comprises outer terminals on a bottom surface of the semiconductor substrate (items 140 are on a bottom surface of item 100),
wherein non-conductive layers fill a space between the semiconductor substrate and the lowermost one of the semiconductor chips and spaces between the semiconductor chips (non-conductive layer fill items 415, 425a,425b and 435 fill spaces between semiconductor chips of item 200 and between the lowermost semiconductor chip in item 200 and substrate item 100), and
wherein a width of each of the outer terminals is equal than a width of each of the chip terminals.
856 does not teach about a semiconductor package, wherein a width of each of the outer terminals is greater than a width of each of the chip terminals.
It would have been an obvious matter of design choice to experiment using different widths for the outer and chip terminals, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding Claim 17. 856 teaches in Fig. 5 about a semiconductor package, wherein the semiconductor substrate further comprises lower substrate pads on a bottom surface of the semiconductor substrate (lower substrate pad items 145 are located on a bottom surface of item 100),
wherein each of the semiconductor chips further comprises lower chip pads on a bottom surface of each of the semiconductor chips (lower chip pad items 217,227a,227b and 237 are located on a bottom surface of the semiconductor chips), and
wherein a third width of each of the lower substrate pads is equal than a fourth width of each of the lower chip pads.
856 does not teach about a semiconductor package, wherein a third width of each of the lower substrate pads is greater than a fourth width of each of the lower chip pads.
It would have been an obvious matter of design choice to experiment using different relative widths for the lower substrate and chip pads, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding Claim 18. 856 teaches in Fig. 5 about a semiconductor package, wherein the second semiconductor chip comprises a chip, a type of the chip being same as a type of each of the first semiconductor chips (“the plurality of semiconductor chips 210, 220a, 220b and 230 may be memory chips”, [0019], Ln. 6-7).
Regarding Claim 19. 856 teaches in Fig. 5 about a semiconductor package, wherein a number of the first semiconductor chips included in the chip stack is 3 (items 210,220a and 220b).
856 does not teach about a semiconductor package, wherein a number of the first semiconductor chips included in the chip stack ranges from 3 to 15.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to experiment with a different number of first semiconductor chips within a chip stack, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897
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