DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 (which read on claims 1-7, 9, 11-13, 15-17, and 19-20) in the reply filed on 5/5/2026 is acknowledged.
Claims 8, 10, and 18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claims 11-15 are allowable. The restriction requirement among Species 1, 2, and 3, as set forth in the Office action mailed on 4/28/2026, has been reconsidered in view of the allowability of claims to the elected invention pursuant to MPEP § 821.04(a). The restriction requirement is hereby withdrawn as to any claim that requires all the limitations of an allowable claim. Specifically, the restriction requirement of 4/28/2026 is partially withdrawn. Claim 14, directed to Species 2, is no longer withdrawn from consideration because the claim(s) requires all the limitations of an allowable claim. However, claims 8, 10, and 18, directed to Species 2 and 3 remain withdrawn from consideration because they do not all require all the limitations of an allowable claim.
In view of the above noted withdrawal of the restriction requirement, applicant is advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
Once a restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 9, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20240282671) in view of Liao et al. (US 20240021497).
Regarding claim 1, Chen teaches, in Figs. 2 and 13, a semiconductor device ([0027]-[0028], [0039]), comprising:
a substrate (50, [0040], labelled in Fig. 12) including a first dummy region (Fig. 2, right 18DM, [0028]; see Fig. 12 for cross-section view of 18DM) and a second dummy region (Fig. 2, middle 18DM, [0028]) spaced apart from each other and a trench (filled by second from right 16, Figs. 2 and 13, [0026]) between the first dummy region (right 18DM) and the second dummy region (middle 18DM) (see Fig. 2);
a device isolation layer (34', Fig. 13, labelled in Fig. 11, [0046]-[0047]) filling the trench (see Fig. 13) between the first dummy region (right 18DM) and the second dummy region (middle 18DM);
a dielectric structure (38’, labelled in Fig. 11, surrounding second from right 16 in Fig. 2, [0046]-[0047], Fig. 13) on the device isolation layer (34') (see Fig. 13);
an interlayer dielectric layer (61, [0051]) on the dielectric structure (38') (see Fig. 13);
a power line (12FS/22FS, [0054]) on the interlayer dielectric layer (61) (see Fig. 13);
a power delivery network layer (12BS/22BS, [0056], the backside power lines are functionally a power delivery network) on a bottom surface of the substrate (50) (see Fig. 13); and
a through via (16, [0026]) extending from the backside power lines (12BS/22BS) through the dielectric structure (38') to the power line (12FS/22FS) (see Fig. 13).
Chen does not teach that an upper portion of the device isolation layer includes a protrusion and a trough, and that the dielectric structure covers the protrusion and the trough.
In a similar field of endeavor, Liao teaches, in Fig. 2ZJ-1, that an upper (for flipped Fig. 2ZJ-1) portion of the device isolation layer (112, Fig. 13, [0049], Fig. 2ZJ-1) includes a protrusion and a trough (see annotated Fig. 2ZJ-1 below), and
that the dielectric structure (135/142/144, [0060], [0063]) covers the protrusion and the trough,
in order to improve production efficiency ([0001]) and improve isolation of the through via from the surrounding electrodes.
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Liao Fig. 2ZJ-1
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the dielectric structure of Chen with the dielectric structure shape of Liao, in order to improve production efficiency ([0001]) and improve isolation of the through via from the surrounding electrodes.
Regarding claim 2, Chen in view of Liao teaches the limitations of claim 1. Liao further teaches that the dielectric structure (135/142/144, Fig. 2ZJ-1) includes a first dielectric structure (135/142) and a second dielectric structure (144) on the first dielectric structure,
the first dielectric structure and the second dielectric structure each include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer ([0061], [0064], [0065]).
Regarding claim 3, Chen in view of Liao teaches the limitations of claim 1. Liao further teaches that a height of the trough is lower than a height of a top surface (for flipped Fig. 2ZJ-1, topmost height where protrusion is) of the device isolation layer (112) (see annotated Fig. 2ZJ-1 above).
Regarding claim 9, Chen in view of Liao teaches the limitations of claim 1. Liao further teaches that the protrusion is adjacent to at least one side (left and right side) of the through via (190/290, [0120]) (see annotated Fig. 2ZJ-1 above).
Regarding claim 16, Chen teaches, in Figs. 2 and 13, a semiconductor device ([0027]-[0028], [0039]), comprising:
a logic cell (20, [0028], see Fig. 2) and a tap cell (10, [0028], see Fig. 2) on a substrate (50, labelled in Fig. 12, [0040]),
the substrate (50) including a first active region (18ACT of 62N, [0053]), a second active region (18ACT of 62P, [0053]) (see Fig. 13), a first dummy region (right 18DM, Fig. 2, [0028]), and a second dummy region (middle 18DM, Fig. 2, [0028]) (see Fig. 12 for cross-section view of 18DM);
a metal layer (including 12FS/22FS, 76, 14FS/24FS, and 74; see Fig. 13, [0054]) on the logic cell (20) and the tap cell (10), the metal layer including a power line (12FS/22FS, [0054]); and
a power delivery network layer (12BS/22BS, [0056], the backside power lines are functionally a power delivery network) on a bottom surface of the substrate (50) (see Fig. 13),
wherein the logic cell (20) includes
a first active region (18ACT of 62N) and a second active region (18ACT of 62P) (Fig. 13, [0053]),
a gate electrode (58, [0055]) on the first active region (62N) and the second active region (62P) (see Fig. 13),
an active contact (66, [0051]) adjacent to one side of the gate electrode (58) (see Fig. 13), and
a gate contact (68, [0051]) coupled to the gate electrode (58) (see Fig. 13),
wherein the tap cell (10) includes
a first dummy region (right 18DM, Fig. 2, [0028]) and a second dummy region (middle 18DM, Fig. 2, [0028]),
a dummy electrode on the first dummy region and the second dummy region ([0028], “dummy replacement gate stacks” in each 18DM),
a dielectric structure (38’, labelled in Fig. 11, surrounding second from right 16 in Fig. 2, [0046]-[0047], Fig. 13) between the first dummy region (right 18DM) and the second dummy regions (middle 18DM), and
a through via (16, Figs. 2 and 13, [0026]) that extends from the backside power lines (12BS/22BS) through the dielectric structure (34/38) to the power line (12FS/22FS) (see Fig. 13).
Chen does not teach that a bottom surface of the dielectric structure has a wavy profile.
In a similar field of endeavor, Liao teaches, in Fig. 2ZJ-1, that a bottom surface (for flipped Fig. 2ZJ-1) of the dielectric structure (128/135/142/144; [0124], [0060], and [0063]) has a wavy profile, in order to improve production efficiency ([0001]) and improve isolation of the through via from the surrounding electrodes.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the dielectric structure of Chen with the dielectric structure shape of Liao, in order to improve production efficiency ([0001]) and improve isolation of the through via from the surrounding electrodes.
Regarding claim 17, Chen in view of Liao teaches the limitations of claim 16. Chen further teaches, in Figs. 2 and 13, that the substrate (50) further includes a trench (filled by second from right 16, Figs. 2 and 13, [0026]) between the first dummy region (right 18DM) and the second dummy region (middle 18DM) (see Fig. 2),
the tap cell further includes a device isolation layer (34', Fig. 13, labelled in Fig. 11, [0046]-[0047]) filling the trench (see Fig. 13) between the first dummy region (right 18DM) and the second dummy region (middle 18DM),
Liao further teaches that an upper (for flipped Fig. 2ZJ-1) portion of the device isolation layer (112, Fig. 13, [0049], Fig. 2ZJ-1) includes a protrusion and a trough (see annotated Fig. 2ZJ-1 below), and
the bottom surface of the dielectric structure (128/135/142/144) covers the protrusion and the trough (see annotated Fig. 2ZJ-1 below).
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Liao Fig. 2ZJ-1
Claims 6-7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20240282671) in view of Liao et al. (US 20240021497), and further in view of Lanzillo et al. (US 20240105608).
Regarding claim 6, Chen in view of Liao teaches the limitations of claim 1. Chen in view of Liao does not teach that the power line includes an extension on the dielectric structure, a width of the extension is greater than a line-width of the power line, and the through via is connected to the extension.
In a similar field of endeavor, Lanzillo teaches, in Figs. 3-4, that
the power line (120/114/114A, [0035]) includes an extension (114A, [0034]) on the dielectric structure (in 130, [0033]),
a width of the extension (114A) is greater than a line-width of the power line ([0034]), and
the through via (108) is connected to the extension (114A),
in order to have a wider through via and thus lower its resistance ([0037]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the power line shape of Chen in view of Liao with the power line shape of Lanzillo, in order to have a wider through via and thus lower its resistance ([0037]).
Regarding claim 7, Chen in view of Liao and Lanzillo teaches the limitations of claim 1. Lanzillo further teaches, in Fig. 3, that the extension (114A) vertically overlaps the dielectric structure (surrounding 108 within 130).
Regarding claim 20, Chen in view of Liao teaches the limitations of claim 16. Chen in view of Liao does not teach that the power line includes an extension on the dielectric structure, a width of the extension is greater than a line-width of the power line, and the through via is connected to the extension.
In a similar field of endeavor, Lanzillo teaches, in Figs. 3-4, that
the power line (120/114/114A, [0035]) includes an extension (114A, [0034]) on the dielectric structure (in 130, [0033]),
a width of the extension (114A) is greater than a line-width of the power line ([0034]), and
the through via (108) is connected to the extension (114A),
in order to have a wider through via and thus lower its resistance ([0037]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the power line shape of Chen in view of Liao with the power line shape of Lanzillo, in order to have a wider through via and thus lower its resistance ([0037]).
Allowable Subject Matter
Claims 11-15 are allowed.
Claims 4-5 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, the closest prior art is Chen et al. (US 20240282671) in view of Liao et al. (US 20240021497), which teaches most limitations of the claim. However, the limitation “a pitch between the plurality of dummy electrodes is a first pitch, a pitch between the plurality of protrusions is a second pitch, and the second pitch is equal to the first pitch” would not have been obvious in view of the closest prior art.
Claims 12-15 are allowed as they depend from allowed independent base claim 11.
Regarding claim 4, the closest prior art is Chen et al. (US 20240282671) in view of Liao et al. (US 20240021497), which teaches the limitations of claim 1. However, the limitation “a pitch between the plurality of dummy electrodes is a first pitch, the protrusion includes a plurality of protrusions, a pitch between the plurality of protrusions is a second pitch, and the second pitch is equal to the first pitch” would not have been obvious in view of the closest prior art.
Claim 5 is allowed as it depends from claim 4.
Regarding claim 19, the closest prior art is Chen et al. (US 20240282671) in view of Liao et al. (US 20240021497), which teaches the limitations of claim 17. However, the limitation “a pitch between the plurality of dummy electrodes is a first pitch, the protrusion is one protrusion among a plurality of protrusions included in the upper portion of the device isolation layer, a pitch between the plurality of protrusions is a second pitch, and the second pitch is equal to the first pitch” would not have been obvious in view of the closest prior art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is 703-756-4644. The examiner can normally be reached Monday - Friday 12:30-9:30 PM ET.
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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