DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed May 11, 2026. Claims 1, 11, and 17 have been amended. No claims have been added. No claims have been canceled. Currently, claims 1-20 are pending.
Applicant’s Amendments to the specification overcome the drawing objection outlined in the previous Office Action. The drawing objection has been withdrawn.
Response to Arguments
Applicant’s arguments with respect to claims 1, 11, and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 17 is objected to because of the following informalities:
In line 14: “un upper” should read --an upper--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20210234002 A1) herein after “Lee” in view of Wada (US 20230326752 A1).
Regarding claim 1, Figs. 5-6, and 11 of Lee disclose a semiconductor device (Fig. 11, semiconductor device 400, ¶ [0030]) comprising:
a semiconductor substrate (Fig. 5, wafer 100, ¶ [0022]);
source/drain patterns (Fig. 11, source/drain features 404, ¶ [0034]) spaced apart in a first direction (Y-direction in Fig. 6, terrace direction T in Fig. 11) on the semiconductor substrate (100);
and channel patterns (Fig. 11, active region 402, ¶ [0034]) on the semiconductor substrate (100), wherein at least one of the channel patterns (402) is between adjacent source/drain patterns (404) among the source/drain patterns (404),
wherein at least one of the channel patterns (402) includes a plurality of semiconductor patterns (Fig. 11, plurality of channel members 408, ¶ [0035]), and the plurality of semiconductor patterns (408) are spaced apart from each other in a second direction (Z-direction in Fig. 6, vertical direction in Fig. 11) that is perpendicular to an upper surface of the semiconductor substrate (100),
wherein at least one of the channel patterns (Fig. 5, “the second epitaxial layer 130 may be referred to as a channel layer”, ¶ [0026]) includes a surface pattern (shown in Fig. 5), wherein the surface pattern (shown in Fig. 5) includes first surfaces (see Annotation 1, Fig. 5 of Lee, S3) and second surfaces (see Annotation 1, Fig. 5 of Lee, S4),
wherein the first surfaces (S3) include protruding edges (see Annotation 1, Fig. 5 of Lee, E2),
wherein the second surfaces (S4) are respectively connected to the first surfaces (S3) through protruding edges (E2), and
wherein the protruding edges (E2) are arranged in a third direction (X-direction in Fig. 5).
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Annotation 1, Fig. 5 of Lee
Lee fails to disclose wherein the upper surface of the semiconductor substrate includes a {110} crystal plane.
In the similar field of endeavor of finFETs, Wada discloses wherein the upper surface of the semiconductor substrate includes a {110} crystal plane (“the silicon substrate cut from {110} plane crystal”, ¶ [0012]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Lee with the directions as disclosed by Wada, to obtain desired carrier mobility (see Wada, ¶ [0055]).
Regarding claim 2, Lee and Wada together disclose the semiconductor device of claim 1 as applied above, and Fig. 1 of Lee further discloses wherein the third direction (X) is in a same direction as a fourth direction perpendicular to the first direction (Y) or is 30° or less with respect to the fourth direction (“the tile angle θ may be between about 1° and about 4°”, “the tilt angle θ with respect to the X direction”, ¶ [0022-0023]).
Regarding claim 3, Lee and Wada together disclose the semiconductor device of claim 1 as applied above, but Lee fails to disclose wherein the first direction is in a <110>
direction, and wherein the fourth direction is in a <100> direction.
In the similar field of endeavor of fin field effect transistors, Figs. 6A-6B of Wada disclose wherein the first direction is in a <110> direction, and wherein the fourth direction is in a <100> direction (Figs. 6A-6B, “a {110} silicon substrate from a crystal set in a 3-dimensional axis (X, Y, Z axes), if the direction of the crystal growth is set along the Z-axis (in the <110> orientation), then the silicon substrate cut from the crystal is in the X-Y plane, which is orthogonal to the Z-axis. Here, the X-axis is aligned in the <100> orientation and Y-axis in <110> orientation”, ¶ [0052]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Lee with the directions as disclosed by Wada, to obtain desired carrier mobility (see Wada, ¶ [0055]).
Regarding claim 4, Lee and Wada together disclose the semiconductor device of claim 1 as applied above, and Fig. 5 of Lee further discloses wherein a length (Fig. 5, step height S, ¶ [0023]) of at least one of the second surfaces (S4) is 1.9Å to 38Å (“a step height S along the Z direction, which may be between about 2 Å and about 3 Å”, ¶ [0023]).
Regarding claim 5, Lee and Wada together disclose the semiconductor device of claim 1 as applied above, and Fig. 6 of Lee further discloses wherein a carrier moving direction (Y) in the channel patterns (402) is the first direction (Y) (“charge carriers travel along the terrace direction T in the second epitaxial layer 130”, ¶ [0028]).
Regarding claim 6, Lee and Wada together disclose the semiconductor device of claim 1 as applied above, and Fig. 5 of Lee further discloses comprising an epitaxial layer (Fig. 5, epitaxial layer 120, ¶ [0026]) on the semiconductor substrate (100).
Lee fails to disclose wherein the epitaxial layer includes a { 110} crystal plane.
In the similar field of endeavor of finFETs, Wada discloses wherein the epitaxial layer includes a {110} crystal plane (“the preferred silicon substrate, on the surface of which the epitaxial layer is grown, according to the present invention is a silicon substrate cut from the {110} plane”, ¶ [0046]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Lee with the directions as disclosed by Wada, to obtain desired carrier mobility (see Wada, ¶ [0055]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20210234002 A1) and Wada (US 20230326752 A1) in further view of Masuda et al. (US 20090230404 A1) herein after “Masuda”.
Regarding claim 7, Lee and Wada together disclose the semiconductor device of claim 6 as applied above, but the combination fails to disclose wherein a distance between adjacent protruding edges among the protruding edges is 20 nm to 300 nm.
In the similar field of endeavor of MOSFETs, Fig. 2 of Masuda discloses wherein a distance between adjacent protruding edges among the protruding edges is 20 nm to 300 nm (Fig. 2, “The length P1 of one period of facet 1 is 100 nm or more”, ¶ [0058]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Lee with the protruding edges as disclosed by Masuda, to improve carrier mobility (see Masuda, ¶ [0085]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20210234002 A1) and Wada (US 20230326752 A1) in view of Wang et al. (US 20220359396 A1) herein after “Wang”.
Regarding claim 8, Lee and Wada together disclose the semiconductor device of claim 1 as applied above, but the combination fail to disclose comprising a diffusion barrier layer on a lower surface of the semiconductor substrate.
In the similar field of endeavor of fin field effect transistors, Fig. 29 of Wang discloses comprising a diffusion barrier layer (Fig. 29, dielectric layer 152, ¶ [0092]) on a lower surface of the semiconductor substrate (Fig. 29, fins 54, ¶ [0014]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Lee with the diffusion barrier layer as disclosed by Wang, to isolate the contacts (see Wang, ¶ [0068]).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20210234002 A1) and Wada (US 20230326752 A1) in view of Kato et al. (US 20120326268 A1) herein after “Kato”.
Regarding claim 9, Lee and Wada together disclose the semiconductor device of claim 1 as applied above, but the combination fails to disclose wherein the semiconductor substrate includes impurities, and
wherein the impurities include nitrogen, boron, gallium, indium, phosphorus, arsenic, and/or antimony.
In the similar field of endeavor of silicon epitaxial wafers, Figs. 2 and 7 of Kato disclose wherein the semiconductor substrate (Fig. 2, silicon epitaxial wafer W, ¶ [0047]) includes impurities, and
wherein the impurities include nitrogen, boron, gallium, indium, phosphorus, arsenic, and/or antimony (“dopant such as phosphorus”, ¶ [0052]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Lee with the doping as disclosed by Kato, to achieve desired doping while reducing surface irregularities (see Kato, ¶ [0053]).
Regarding claim 10, Lee, Wada and Kato together disclose the semiconductor device of claim 9 as applied above, but Lee fails to disclose wherein a concentration of the impurities is 1.00E^+18/cm3 to 1.00E^+20/cm3.
In the similar field of endeavor of silicon epitaxial wafers, Kato discloses impurities is 1.00E^+18/cm3 to 1.00E^+20/cm3 (“phosphorus concentration of 1.times.10.sup.19/cm.sup.3 or more”, ¶ [0053]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Lee with the doping as disclosed by Kato, to achieve desired doping while reducing surface irregularities (see Kato, ¶ [0053]).
Claims 11-15, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20210234002 A1) and Wada (US 20230326752 A1) in further view of Wang (US 20220359396 A1).
Regarding claim 11, Figs. 5-6, and 11 of Lee disclose a semiconductor device (Fig. 11, semiconductor device 400, ¶ [0030]) comprising:
a semiconductor substrate (100);
an epitaxial layer (120) on the semiconductor substrate (100);
source/drain patterns (404) spaced apart in a first direction (Y) on the epitaxial layer (120);
channel patterns (402) on the epitaxial layer (120), wherein at least one of the channel patterns (402) is between adjacent source/drain patterns (404) among the source/drain patterns (404);
a gate electrode (Fig. 11, gate structure 406, ¶ [0034]) on at least one of the channel patterns (402);
a gate insulating layer between the gate electrode (406) and the channel patterns (402) (“the gate structure 406 may include an interfacial layer to interface the channel members 408, a gate dielectric layer over the interfacial layers”, ¶ [0035]);
wherein an upper surface of the semiconductor substrate (100) is inclined from the first surface by a crystal off angle (“the tile angle θ may be between about 1° and about 4°”, “the tilt angle θ with respect to the X direction”, ¶ [0022-0023]).
Lee fails to disclose an interlayer insulating layer on the gate insulating layer; and
active contacts electrically connected to the source/drain patterns through the interlayer insulating layer,
wherein the semiconductor substrate includes a first surface that comprises a {110} crystal plane,
wherein the epitaxial layer includes a second surface that comprises a {110} crystal plane, the second surface being at least one of an upper surface and a lower surface of the epitaxial layer.
In the similar field of endeavor of finFETs, Wada discloses wherein the semiconductor substrate includes a first surface that comprises a {110} crystal plane (“the silicon substrate cut from {110} plane crystal”, ¶ [0012]),
wherein the epitaxial layer includes a second surface that comprises a {110} crystal plane, the second surface being at least one of an upper surface and a lower surface of the epitaxial layer (“the preferred silicon substrate, on the surface of which the epitaxial layer is grown, according to the present invention is a silicon substrate cut from the {110} plane”, ¶ [0046]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Lee with the directions as disclosed by Wada, to obtain desired carrier mobility (see Wada, ¶ [0055]).
Wada fails to disclose an interlayer insulating layer on the gate insulating layer; and
active contacts electrically connected to the source/drain patterns through the interlayer insulating layer.
In the similar field of endeavor of fin field effect transistors, Fig. 29 of Wang discloses an interlayer insulating layer (Fig. 29, second ILD 122, ¶ [0079) on the gate insulating layer (Fig. 29, gate dielectrics 102, ¶ [0015]); and
active contacts (Fig. 29, source/drain contacts 126, ¶ [0080]) electrically connected to the source/drain patterns (92) through the interlayer insulating layer (122).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Lee with the interlayer and contacts as disclosed by Wang, to increase performance and optimize device layout (see Wang, ¶ [0012]).
Regarding claim 12, Lee, Wada and Wang together disclose the semiconductor device of claim 11 as applied above, and Lee further discloses wherein the crystal off angle is 5° or less (“the tile angle θ may be between about 1° and about 4°”, ¶ [0022]).
Regarding claim 13, Lee, Wada and Wang together disclose the semiconductor device of claim 11 as applied above, and Lee further discloses wherein the upper surface of the semiconductor substrate (100) is tilted by a direction off angle in a second direction (Z) that is a <100> direction with respect to the first surface and is inclined by the crystal off angle (“the Z direction may be parallel to the [100] crystal direction “, “The wafer 100 with a non-zero tilt angle θ may be referred to as an off-axis wafer 100”, ¶ [0021-0022]).
Regarding claim 14, Lee, Wada and Wang together disclose the semiconductor device of claim 13 as applied above, and Lee further discloses wherein the direction off angle is 30° or less (“the tile angle θ may be between about 1° and about 4°”, “the tilt angle θ with respect to the X direction”, ¶ [0022-0023]).
Regarding claim 15, Lee, Wada and Wang together disclose the semiconductor device of claim 13 as applied above, and Lee further discloses wherein the second direction (Z) is perpendicular to a carrier moving direction (Y) in the channel patterns (402) (“charge carriers travel along the terrace direction T in the second epitaxial layer 130”, ¶ [0028]).
Regarding claim 17, Figs. 5-6, and 11 of Lee02 disclose a semiconductor device (Fig. 11, semiconductor device 400, ¶ [0030]) comprising:
an epitaxial layer (120);
source/drain patterns (404) spaced apart in a first direction (Y) on the epitaxial layer (120); and
channel patterns (402) on the epitaxial layer (120), wherein at least one of the channel patterns (402) is between adjacent source/drain patterns (404) among the source/drain patterns (404);
a gate electrode (406) on at least one of the channel patterns (402);
a gate insulating layer between the gate electrode (406) and the channel patterns (402) (“the gate structure 406 may include an interfacial layer to interface the channel members 408, a gate dielectric layer over the interfacial layers”, ¶ [0035]);
wherein the epitaxial layer (120) includes a first surface pattern (shown in Fig. 5) that includes first edges protruding in a second direction (Z) perpendicular to the first direction (Y),
wherein the first surface pattern (shown in Fig. 5) includes first surfaces (see Annotation 1, Fig. 5 of Lee, S1) and second surfaces (see Annotation 1, Fig. 5 of Lee, S2) that are respectively connected to the first surfaces (S1) through the first edges (see Annotation 1, Fig. 5 of Lee, E1),
wherein at least one of the channel patterns (402) includes a second surface pattern (shown in Fig. 5) that includes second edges (E2) protruding in the second direction (Z), and
wherein the second surface pattern (shown in Fig. 5) includes third surfaces (S3) and fourth surfaces (S4) that are respectively connected to the third surfaces (S3) through the second edges (E2).
Lee fails to disclose an interlayer insulating layer on the gate insulating layer; and
active contacts electrically connected to the source/drain patterns through the interlayer insulating layer;
a lower power wiring on a lower surface of the epitaxial layer; and
a back contact electrically connecting the lower power wiring and the source/drain patterns through the epitaxial layer,
wherein at least one of un upper surface and a lower surface of the epitaxial layer comprises a {110} crystal plane.
In the similar field of endeavor of finFETs, Wada discloses wherein at least one of un upper surface and a lower surface of the epitaxial layer comprises a {110} crystal plane (“the preferred silicon substrate, on the surface of which the epitaxial layer is grown, according to the present invention is a silicon substrate cut from the {110} plane”, ¶ [0046]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Lee with the directions as disclosed by Wada, to obtain desired carrier mobility (see Wada, ¶ [0055]).
Wada fails to disclose an interlayer insulating layer on the gate insulating layer; and
active contacts electrically connected to the source/drain patterns through the interlayer insulating layer;
a lower power wiring on a lower surface of the epitaxial layer; and
a back contact electrically connecting the lower power wiring and the source/drain patterns through the epitaxial layer.
In the similar field of endeavor of fin field effect transistors, Fig. 29 of Wang discloses an interlayer insulating layer (122) on the gate insulating layer (102); and
active contacts (126) electrically connected to the source/drain patterns (92) through the interlayer insulating layer (122);
a lower power wiring (Fig. 29, conductive features 160, ¶ [0096]) on a lower surface of the epitaxial layer (54); and
a back contact (Fig. 29, power rail contacts 158, ¶ [0095]) electrically connecting the lower power wiring (160) and the source/drain patterns (92) through the epitaxial layer (54).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Lee with the contacts as disclosed by Wang, to increase performance and optimize device layout (see Wang, ¶ [0012]).
Regarding claim 18, Lee, Wada and Wang together disclose the semiconductor device of claim 17 as applied above, but Lee and Wada fail to disclose comprising a power transmission network layer on the lower power wiring.
In the similar field of endeavor of fin field effect transistors, Fig. 29 of Wang discloses comprising a power transmission network layer on the lower power wiring (“Some or all of the conductive features 160 are power rails 160P, which are conductive lines that electrically connect the epitaxial source/drain regions 92P to a reference voltage, supply voltage, or the like”, ¶ [0098]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Lee with the contacts as disclosed by Wang, to increase performance and optimize device layout (see Wang, ¶ [0012]).
Regarding claim 19, Lee, Wada and Wang together disclose the semiconductor device of claim 17 as applied above, but Lee and Wada fail to disclose comprising a diffusion barrier between the lower surface of the epitaxial layer and the lower power wiring.
In the similar field of endeavor of fin field effect transistors, Fig. 29 of Wang discloses comprising a diffusion barrier (152) between the lower surface of the epitaxial layer (154) and the lower power wiring (160).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Lee with the diffusion barrier layer as disclosed by Wang, to isolate the contacts (see Wang, ¶ [0068]).
Regarding claim 20, Lee, Wada and Wang together disclose the semiconductor device of claim 17 as applied above, and Fig. 5 of Lee further discloses wherein two or more of the first surfaces (S1) and the third surfaces (S3) are disposed in the second direction (Z).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20210234002 A1), Wada (US 20230326752 A1) and Wang (US 20220359396 A1) in further view of Chen et al. (US 20190139956 A1) herein after “Chen”.
Regarding claim 16, Lee, Wada and Wang together disclose the semiconductor device of claim 11 as applied above, but the combination fails to disclose wherein the epitaxial layer includes impurities, and
wherein the impurities include boron, gallium, indium, phosphorus, arsenic, and/or antimony, and a concentration of the impurities included in the epitaxial layer is 1.00E+14/cm3 to 5.00E+14/cm3.
In the similar field of endeavor of fin-type field effect transistors, Fig. 1B of Chen discloses wherein the epitaxial layer (Fig. 1B, semiconductor fins 208b, ¶ [0015]) includes impurities, and
wherein the impurities include boron, gallium, indium, phosphorus, arsenic, and/or antimony (“the doped regions may be doped with p-type dopants, such as boron or BF.sub.2; n-type dopants, such as phosphorus or arsenic”, ¶ [0013]), and a concentration of the impurities included in the epitaxial layer (120) is 1.00E^+14/cm3 to 5.00E^+14/cm3 (“the dopant concentration within the second semiconductor fins 208b may be 2×10.sup.12 atom/cm.sup.2 to 5×10.sup.14 atom/cm.sup.2”, ¶ [0016]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Lee with the epitaxial layer as disclosed by Chen, to obtain the desired electrical characteristics (see Chen, ¶ [0013]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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