DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-11 & 17-20 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Srivastava et al (US20210018969).
Regarding claim 1, Srivastava discloses a non-transitory computer readable medium comprising stored instructions(FIG 4 & 6), which when executed by a processor(110), cause the processor to: convert an input clockwide pulse received from an upstream circuit running in a first clock domain into an output clockwide pulse that is synchronized to a second clock domain(FIG 6-7; 162 receiving input REQ_1 pd_clk1 and convert to an output clockwide pulse ACK_1 being processed by 169 that is sync to a second clock domain pd_clk2 e.g., ACK_2 sync being processed by 169 and final output as ACK); and advance a count in response to the output clockwide pulse that is input to a pointer counter synchronized to the second clock domain (FIG 6 & 13; a point counter 166 receiving clock pd_clk2 and outputting counter overflow that is synced with ACK_2 in final output as ACK, Steps 210(using 166…), 212 and 214 ACK).
Regarding claim 2, Srivastava discloses wherein the input clockwide pulse is converted using a pulse-to-pulse synchronizing circuit that is one of a plurality of pulse-to-pulse synchronizing circuits(162 164), and each pulse-to-pulse synchronizing circuit of the plurality of pulse-to- pulse synchronizing circuits has a corresponding output to output a corresponding output clockwide pulse (ACK_1 ACK_2 into 169 fed into 170 and outputted as ACK).
Regarding claim 3, Srivastava discloses wherein the count is advanced by a number that is equal to a number of output clockwide pulses asserted by the plurality of pulse-to-pulse synchronizing circuits (FIG 6; ACK_1 ACK_2 into 169 fed into 170 and outputted as ACK).
Regarding claim 4, Srivastava discloses wherein the stored instructions further cause the processor to: drive the plurality of pulse-to-pulse synchronizing circuits and cycle through the output clockwide pulses in a manner that avoids exceeding a bandwidth of the plurality of pulse-to-pulse synchronizing circuits (FIG 6-7; 162 164 ACK_1 ACK_2 … pulse signals on FIG 7 according to the cycle).
Regarding claim 5, Srivastava discloses wherein a first clock frequency of the first clock domain is higher than a second clock frequency of the second clock domain (FIG 7 & 13; first clock domain e.g., at 212, and slower clock frequency s210 e.g., timeout being generated based on pd_ck2 signal).
Regarding claim 6, Srivastava discloses wherein a first clock frequency of the first clock domain is lower than a second clock frequency of the second clock domain (FIG 7; pd_ck1 signal lower than pd_ck2 signal e.g., time).
Regarding claim 7, Srivastava discloses wherein a first clock frequency of the first clock domain is equal to a second clock frequency of the second clock domain, but a phase relationship between the first clock domain and the second clock domain is different (FIG 7 & 13; same frequency in step 204 prior to generating a timeout value e.g., 206 different phases after resetting the data path logic for clock domains).
Regarding claim 8, Srivastava discloses wherein the processor comprises a component of a synchronizing first-in-first-out buffer, and the count indicates a pointer pointing to a location in the synchronizing first-in-first out buffer at which a data word is stored (FIG 7 & 13; 166 indicating timeout step 210 and buffer 169 data stored being received from 162 164 in sync with output timeout_sync).
Regarding claim 9, Srivastava discloses wherein the synchronizing first-in-first-out buffer receives a plurality of input words of data in a single input clock period (FIG 6-7; 169 receiving plurality of input words of data e.g., ACK_1 ACK_2 in clock period high).
Regarding claim 10, Srivastava discloses wherein the synchronizing first-in-first-out buffer provides a plurality of output words to a downstream circuit in a single output clock period (FIG 6-7; 169 receiving plurality of input words of data e.g., ACK_1 ACK_2 in clock period low).
Regarding claim 17, Srivastava discloses method comprising: receiving an electronic signal comprising a single clockwide pulse in a first clock domain that runs at a first clock frequency; converting the single clockwide pulse in the first clock domain to a single clockwide pulse in a second clock domain that runs at a second clock frequency(FIG 6-7; 162 receiving input REQ_1 pd_clk1 and convert to an output clockwide pulse ACK_1 being processed by 169 that is sync to a second clock domain pd_clk2 e.g., ACK_2 sync being processed by 169 and final output as ACK); advancing a count in response to the single clockwide pulse in the second clock domain that is input to a pointer counter synchronized to the second clock domain (FIG 6; a point counter 166 receiving clock pd_clk2 and outputting counter overflow that is synced with ACK_2 in final output as ACK); and outputting a pointer associated with the electronic signal based on the count(FIG 6 & 13; Steps 210(using 166…), 212 and 214 ACK).
Regarding claim 18, Srivastava discloses wherein the first clock frequency is higher than the second clock frequency(FIG 7 & 13; first clock domain e.g., at 212, and slower clock frequency s210 e.g., timeout being generated based on pd_ck2 signal), and the method further comprises: generating, by the processing device in response to the receiving but prior to the converting, a plurality of clockwide pulses in proportion to a ratio of the first clock frequency to the second clock frequency (FIG 7 & 13; same frequency in step 204 prior to generating a timeout value for both first and second clock frequency )
Regarding claim 19, Srivastava discloses wherein the first clock frequency is lower than the second clock frequency (FIG 7; pd_ck1 signal lower than pd_ck2 signal e.g., time).
Regarding claim 20, Srivastava discloses wherein the first clock frequency of the first clock domain is equal to the second clock frequency of the second clock domain, but a phase relationship between the first clock domain and the second clock domain is at least one of: unknown, insufficiently constrained, or varying (FIG 7 & 13; same frequency in step 204 prior to generating a timeout value e.g., 206 different phases after resetting the data path logic for clock domains).
Response to Arguments
Applicant’s arguments, see Remark sections pages 7-8, filed 06/26/2026, with respect to the rejection(s) of claim(s) of 1-11 & 17-20 Srivastava et al under 102a(1) have been fully considered but they are not persuasive. the applicant has stated that in page 7 “Srivastava fails to disclose or suggest at least "convert an input clockwide pulse received from an upstream circuit running in a first clock domain into an output clockwide pulse that is synchronized to a second clock domain and advance a count in response to the output clockwide pulse that is input to a pointer counter synchronized to the second clock domain.
In response to the arguments presented above by the applicant, the examiner respectfully disagreed. For example, the examiner clearly has distinguished in the rejection of claim 1 that in FIG 6-7; 162 receiving input REQ_1 pd_clk1 and convert to an output clockwide pulse ACK_1 being processed by 169 that is sync to a second clock domain pd_clk2 e.g., ACK_2 sync being processed by 169 and final output as ACK. Furthermore, clearly Srivastava discloses a point counter 166 receiving clock pd_clk2 and outputting counter overflow that is synced with ACK_2 in final output as ACK. Please note that the pd_CK2 is inputted to pointer 166, and pd_clk1 is inputted to the sync 168 that is outputted to 169 and sync with pd_clk1 at 170 in final output as ACK. Therefore, the rejection under Srivastava et al under 102a(1) is maintained .
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Shirani et al (US6188721 FIG 7 & 13B; discloses latches 390 392, counter 398, generating a pulse every M NS while input is high, 966 granting a clock wide pulse).
Fairbairn et al (US20190157040 FIG 17; [0091] discloses having any changes in votlage from pulse to pulse being synchronized).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUNA A TECHANE/Primary Examiner, Art Unit 2827
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