Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
OFFICE ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) The claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) The claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by the prior art of record Tehranipoor (US 2019/0165935). Regarding claim 1, the prior art discloses:
An IC comprising: IP pieces (fig 1, 3, 7, 9) comprising test logics (Test Patterns), respectively;
a scanner (scan chains/flip-flops/test patterns (fig 4-5 and/or par 14, 32, 37, 54-58, 182) configured to collect debugging data from the test logics of the IP pieces; and
an encryption circuit (summary and/or fig 2, 7-10), configured to convert the debugging data into encrypted data.
(Claim 2) wherein the encryption circuit comprises a first processing circuit configured to obfuscate (fig 4, 7) the debugging data.
(Claim 3) wherein the first processing circuit is further configured to apply an obfuscation pattern (fig 4, 7-8) of the debugging data based on a first seed (first seed is, in terms of, one of input sequence of patterns, test pattern generation, scan test patterns, on-chip true random number generator, signature generation, transmission key generation, simulation, functional activation, as disclosed in this prior art).
(Claim 4) wherein the encryption circuit comprises a second processing circuit configured to rearrange an address of the debugging data (fig 4).
(Claim 5) wherein the second processing circuit is further configured to apply an address rearrangement pattern of the debugging data (fig 4) based on a second seed (second seed is, in terms of, another one of input sequence of patterns, test pattern generation, scan test patterns, on-chip true random number generator, signature generation, transmission key generation, simulation, functional activation, as disclosed in this prior art).
(Claim 6) wherein the encryption circuit (summary and/or fig 2, 7-10) is connected to an output end of the scanner (scan chains/flip-flops/test patterns (fig 4-5 and/or par 14, 32, 37, 54-58, 182).
(Claim 7) wherein the first processing circuit is included in each of the IP pieces (fig 1, 3, 7, 9).
(Claim 8) wherein the second processing circuit is connected to an output end of the scanner (fig 4-5 and/or par 14, 32, 37, 54-58, 182).
(Claim 9) wherein the scanner is configured to form a scan chain by connecting a plurality of scan flip-flops (par 32, 179), and the debugging data includes scan data output from the scan chain.
Claims 10-20 recite similar subject matter and are rejected for the same reason. . For processor/memory/controller/functional blocks/request/security, see fig 1-10 and corresponding text and/or par 2, 33-47, 62, 68, 79, 83-89, 93-94, 183-189, 192-193.
Claims 1-20 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Crouch (US 2011/0083195).
Regarding claim 1, the prior art discloses:
An IC comprising:
IP pieces comprising test logics (par 10-15), respectively;
a scanner (see scan architecture/path/chain/ register in par 10-20) configured to collect debugging data from the test logics of the IP pieces; and
an encryption circuit (fig 25 and/or par 164-171) configured to convert the debugging data into encrypted data.
(Claim 2) wherein the encryption circuit comprises a first processing circuit configured to obfuscate (fig 25 and/or par 164-171) the debugging data.
(Claim 3) wherein the first processing circuit is further configured to apply an obfuscation pattern of the debugging data based on a first seed (fig 25 and/or par 164-171, first seed is, in terms of, one of TDO/TDO, LBIST/MBIST, SHDR, CKDR, UPDR NDI, TDR, TAP, JTAG, signal generator, data to be delivered and extracted from embedded logic/test/functions, scan vectors, disclosed in the prior art and/or fig 10-25 )
(Claim 4) wherein the encryption circuit comprises a second processing circuit configured to rearrange an address of the debugging data (fig 25, scramble/descramble).
(Claim 5) wherein the second processing circuit is further configured to apply an address rearrangement pattern of the debugging data based on a second seed (fig 25 and/or par 164-171, second seed is, in terms of, another one of TDO/TDO, LBIST/MBIST, SHDR, CKDR, UPDR NDI, TDR, TAP, JTAG, signal generator, data to be delivered and extracted from embedded functions/logics/test, scan vectors, as disclosed in the prior art and/or fig 10-25 )
(Claim 6) wherein the encryption circuit is connected to an output end of the scanner (Par 168-181, fig 10-25).
(Claim 7) wherein the first processing circuit is included in each of the IP pieces (par 10-15).
(Claim 8) wherein the second processing circuit is connected to an output end of the scanner (Par 168-181, fig 10-25).
(Claim 9) wherein the scanner is configured to form a scan chain by connecting a plurality of scan flip-flops (fig 3, 6-7, 10-12, 15-21), and the debugging data includes scan data output from the scan chain.
Claims 10-20 recite similar subject matter and are rejected for the same reason. For processor/memory/controller/functional blocks/security, see fig 9-25 and corresponding text.
Claims 1, 10 and 18 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Narayanan (US 2020/0355744). Regarding claim 1, the prior art discloses:
An IC comprising: IP pieces comprising test logics (fig 1-2), respectively;
a scanner (fig 1-2, 5-9) configured to collect debugging data from the test logics of the IP pieces; and
an encryption circuit (fig 5) configured to convert the debugging data into encrypted data.
Claims 10 and 18 recite similar subject matter and are rejected for the same reason.
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL DINH whose telephone number is 571-272-1890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s Supervisor, Jack Chiang can be reached on 571-272-7483. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL DINH/Primary Examiner, Art Unit 2851
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